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slackbuilds-current/academic/verilog
dsomero d0c108251a
various: Update find command to match template. 		12 years ago
..
README academic/verilog: Added to 13.0 repository 16 years ago
slack-desc various: Fix slack-desc formatting and comment nit picks. 12 years ago
verilog.SlackBuild various: Update find command to match template. 12 years ago
verilog.info academic/verilog: Updated for version 0.9.7. 12 years ago

README 

Icarus Verilog is a Verilog simulation and synthesis tool.  It operates as
a compiler, compiling source code written in Verilog (IEEE-1364) into some 
target format.  For batch simulation, the compiler can generate an intermediate
form called vvp assembly.  This intermediate form is executed by the 'vvp' 
command.  For synthesis, the compiler generates netlists in the desired format.