Fix typo.

pcbnew/dialogs/panel_setup_rules_help.md

@@ -283,7 +283,7 @@ For the latter use a `(layer "layer_name")` clause in the rule.
 
 
     # Allow silk intersection with board edge for connectors
-    (rule silk_board_edge_celarance
+    (rule silk_board_edge_clearance
         (constraint silk_clearance)
         (severity ignore)
         (condition "A.memberOfFootprint('J*') && B.Layer=='Edge.Cuts'"))

pcbnew/dialogs/panel_setup_rules_help_md.h

@@ -283,6 +283,13 @@ _HKI( "### Top-level Clauses\n"
 "        (condition \"B.Layer == 'Edge.Cuts'\"))\n"
 "\n"
 "\n"
+"    # Allow silk intersection with board edge for connectors\n"
+"    (rule silk_board_edge_clearance\n"
+"        (constraint silk_clearance)\n"
+"        (severity ignore)\n"
+"        (condition \"A.memberOfFootprint('J*') && B.Layer=='Edge.Cuts'\"))\n"
+"\n"
+"\n"
 "    # Check current-carrying capacity\n"
 "    (rule high-current\n"
 "        (constraint track_width (min 1.0mm))\n"