Add example for silk:board_edge clearance.

Fixes https://gitlab.com/kicad/code/kicad/-/issues/19260

pcbnew/dialogs/panel_setup_rules_help.md

@@ -282,6 +282,13 @@ For the latter use a `(layer "layer_name")` clause in the rule.
         (condition "B.Layer == 'Edge.Cuts'"))
 
 
+    # Allow silk intersection with board edge for connectors
+    (rule silk_board_edge_celarance
+        (constraint silk_clearance)
+        (severity ignore)
+        (condition "A.memberOfFootprint('J*') && B.Layer=='Edge.Cuts'"))
+
+
     # Check current-carrying capacity
     (rule high-current
         (constraint track_width (min 1.0mm))