Browse Source
academic/verilator: Fix slack-desc.
Signed-off-by: Andrew Clemons <andrew.clemons@gmail.com>
pull/186/head
Andrew Clemons
4 years ago
No known key found for this signature in database
GPG Key ID: CD26380FFACBDA2B
1 changed files with
6 additions and
6 deletions
-
academic/verilator/slack-desc
|
|
@ -8,12 +8,12 @@ |
|
|
|
|-----handy-ruler------------------------------------------------------| |
|
|
|
verilator: verilator (the fastest free Verilog HDL simulator) |
|
|
|
verilator: |
|
|
|
verilator: Verilator is invoked with parameters similar to GCC or Synopsys’s VCS. |
|
|
|
verilator: It "Verilates" the specified synthesizable Verilog or SystemVerilog |
|
|
|
verilator: code by reading it, performing lint checks, and optionally inserting |
|
|
|
verilator: assertion checks and coverage-analysis points. It outputs single- or |
|
|
|
verilator: multi-threaded .cpp and .h files, the "Verilated" code. |
|
|
|
verilator: Verilator is invoked with parameters similar to GCC or Synopsys’s |
|
|
|
verilator: VCS. It "Verilates" the specified synthesizable Verilog or |
|
|
|
verilator: SystemVerilog code by reading it, performing lint checks, and |
|
|
|
verilator: optionally inserting assertion checks and coverage-analysis points. |
|
|
|
verilator: It outputs single- or verilator: multi-threaded .cpp and .h files, |
|
|
|
verilator: the "Verilated" code. |
|
|
|
verilator: |
|
|
|
verilator: homepage: https://www.veripool.org/wiki/verilator |
|
|
|
verilator: |
|
|
|
verilator: |