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@ -1,6 +1,6 @@ |
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/***************************************************************************** |
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Copyright (c) 1995, 2014, Oracle and/or its affiliates. All Rights Reserved. |
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Copyright (c) 1995, 2015, Oracle and/or its affiliates. All Rights Reserved. |
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Copyright (c) 2008, Google Inc. |
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Portions of this file contain modifications contributed and copyrighted by |
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@ -38,6 +38,26 @@ Created 9/6/1995 Heikki Tuuri |
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#include "ut0lst.h" |
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#include "sync0types.h" |
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#if defined __i386__ || defined __x86_64__ || defined _M_IX86 \ |
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|| defined _M_X64 || defined __WIN__ |
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#define IB_STRONG_MEMORY_MODEL |
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#endif /* __i386__ || __x86_64__ || _M_IX86 || _M_X64 || __WIN__ */ |
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#ifdef HAVE_WINDOWS_ATOMICS |
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typedef LONG lock_word_t; /*!< On Windows, InterlockedExchange operates |
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on LONG variable */ |
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#elif defined(HAVE_ATOMIC_BUILTINS) && !defined(HAVE_ATOMIC_BUILTINS_BYTE) |
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typedef ulint lock_word_t; |
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#else |
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#define IB_LOCK_WORD_IS_BYTE |
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typedef byte lock_word_t; |
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#endif /* HAVE_WINDOWS_ATOMICS */ |
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#ifdef __WIN__ |
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/** Native event (slow)*/ |
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typedef HANDLE os_native_event_t; |
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@ -429,14 +449,61 @@ amount to decrement. */ |
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# define os_atomic_decrement_uint64(ptr, amount) \ |
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os_atomic_decrement(ptr, amount) |
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/**********************************************************//** |
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Returns the old value of *ptr, atomically sets *ptr to new_val */ |
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# define os_atomic_test_and_set_byte(ptr, new_val) \ |
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__sync_lock_test_and_set(ptr, (byte) new_val) |
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# define os_atomic_test_and_set_ulint(ptr, new_val) \ |
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__sync_lock_test_and_set(ptr, new_val) |
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# if defined(HAVE_IB_GCC_ATOMIC_TEST_AND_SET) |
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/** Do an atomic test-and-set. |
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@param[in,out] ptr Memory location to set to non-zero |
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@return the previous value */ |
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inline |
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lock_word_t |
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os_atomic_test_and_set(volatile lock_word_t* ptr) |
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{ |
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return(__atomic_test_and_set(ptr, __ATOMIC_ACQUIRE)); |
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} |
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/** Do an atomic clear. |
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@param[in,out] ptr Memory location to set to zero */ |
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inline |
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void |
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os_atomic_clear(volatile lock_word_t* ptr) |
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{ |
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__atomic_clear(ptr, __ATOMIC_RELEASE); |
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} |
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# elif defined(IB_STRONG_MEMORY_MODEL) |
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/** Do an atomic test and set. |
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@param[in,out] ptr Memory location to set to non-zero |
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@return the previous value */ |
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inline |
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lock_word_t |
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os_atomic_test_and_set(volatile lock_word_t* ptr) |
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{ |
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return(__sync_lock_test_and_set(ptr, 1)); |
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} |
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/** Do an atomic release. |
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In theory __sync_lock_release should be used to release the lock. |
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Unfortunately, it does not work properly alone. The workaround is |
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that more conservative __sync_lock_test_and_set is used instead. |
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Performance regression was observed at some conditions for Intel |
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architecture. Disable release barrier on Intel architecture for now. |
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@param[in,out] ptr Memory location to write to |
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@return the previous value */ |
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inline |
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lock_word_t |
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os_atomic_clear(volatile lock_word_t* ptr) |
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{ |
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return(__sync_lock_test_and_set(ptr, 0)); |
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} |
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# else |
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# error "Unsupported platform" |
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# endif /* HAVE_IB_GCC_ATOMIC_TEST_AND_SET */ |
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#elif defined(HAVE_IB_SOLARIS_ATOMICS) |
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@ -511,14 +578,51 @@ amount to decrement. */ |
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# define os_atomic_decrement_uint64(ptr, amount) \ |
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os_atomic_increment_uint64(ptr, -(amount)) |
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/**********************************************************//** |
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Returns the old value of *ptr, atomically sets *ptr to new_val */ |
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# define os_atomic_test_and_set_byte(ptr, new_val) \ |
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atomic_swap_uchar(ptr, new_val) |
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# define os_atomic_test_and_set_ulint(ptr, new_val) \ |
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atomic_swap_ulong(ptr, new_val) |
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# ifdef IB_LOCK_WORD_IS_BYTE |
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/** Do an atomic xchg and set to non-zero. |
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@param[in,out] ptr Memory location to set to non-zero |
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@return the previous value */ |
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inline |
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lock_word_t |
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os_atomic_test_and_set(volatile lock_word_t* ptr) |
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{ |
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return(atomic_swap_uchar(ptr, 1)); |
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} |
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/** Do an atomic xchg and set to zero. |
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@param[in,out] ptr Memory location to set to zero |
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@return the previous value */ |
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inline |
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lock_word_t |
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os_atomic_clear(volatile lock_word_t* ptr) |
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{ |
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return(atomic_swap_uchar(ptr, 0)); |
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} |
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# else |
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/** Do an atomic xchg and set to non-zero. |
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@param[in,out] ptr Memory location to set to non-zero |
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@return the previous value */ |
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inline |
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lock_word_t |
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os_atomic_test_and_set(volatile lock_word_t* ptr) |
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{ |
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return(atomic_swap_ulong(ptr, 1)); |
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} |
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/** Do an atomic xchg and set to zero. |
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@param[in,out] ptr Memory location to set to zero |
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@return the previous value */ |
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inline |
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lock_word_t |
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os_atomic_clear(volatile lock_word_t* ptr) |
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{ |
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return(atomic_swap_ulong(ptr, 0)); |
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} |
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# endif /* IB_LOCK_WORD_IS_BYTE */ |
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#elif defined(HAVE_WINDOWS_ATOMICS) |
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@ -633,16 +737,27 @@ amount to decrement. There is no atomic substract function on Windows */ |
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(ib_int64_t*) ptr, \ |
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-(ib_int64_t) amount) - amount)) |
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/**********************************************************//** |
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Returns the old value of *ptr, atomically sets *ptr to new_val. |
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InterlockedExchange() operates on LONG, and the LONG will be |
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clobbered */ |
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# define os_atomic_test_and_set_byte(ptr, new_val) \ |
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((byte) InterlockedExchange(ptr, new_val)) |
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# define os_atomic_test_and_set_ulong(ptr, new_val) \ |
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InterlockedExchange(ptr, new_val) |
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/** Do an atomic test and set. |
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InterlockedExchange() operates on LONG, and the LONG will be clobbered |
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@param[in,out] ptr Memory location to set to non-zero |
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@return the previous value */ |
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inline |
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lock_word_t |
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os_atomic_test_and_set(volatile lock_word_t* ptr) |
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{ |
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return(InterlockedExchange(ptr, 1)); |
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} |
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/** Do an atomic release. |
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InterlockedExchange() operates on LONG, and the LONG will be clobbered |
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@param[in,out] ptr Memory location to set to zero |
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@return the previous value */ |
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inline |
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lock_word_t |
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os_atomic_clear(volatile lock_word_t* ptr) |
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{ |
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return(InterlockedExchange(ptr, 0)); |
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} |
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#else |
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# define IB_ATOMICS_STARTUP_MSG \ |
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@ -692,7 +807,7 @@ for synchronization */ |
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} while (0); |
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/** barrier definitions for memory ordering */ |
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#if defined __i386__ || defined __x86_64__ || defined _M_IX86 || defined _M_X64 || defined __WIN__ |
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#ifdef IB_STRONG_MEMORY_MODEL |
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/* Performance regression was observed at some conditions for Intel |
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architecture. Disable memory barrier for Intel architecture for now. */ |
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# define os_rmb |
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Sergei Golubchik
10 years ago