From 64824a760d3ee4715d301dcdff541b66fac32992 Mon Sep 17 00:00:00 2001 From: Daniel Black Date: Wed, 30 Mar 2016 15:09:52 +1100 Subject: [PATCH] MDEV-8684: UT_RELAX_CPU on Power to non-empty expansion Using __ppc_get_timebase will translate to mfspr instruction The mfspr instruction will block FXU1 until complete but the other Pipelines are available for execution of instructions from other SMT threads on the same core. The latency time to read the timebase SPR is ~10 cycles. So any impact on other threads is limited other FXU1 only instructions (basically other mfspr/mtspr ops). Suggested by Steven J. Munroe, Linux on Power Toolchain Architect, Linux Technology Center IBM Corporation --- storage/innobase/include/ut0ut.h | 5 +++++ storage/xtradb/include/ut0ut.h | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/storage/innobase/include/ut0ut.h b/storage/innobase/include/ut0ut.h index 1dcbae0d132..9ed1a87508c 100644 --- a/storage/innobase/include/ut0ut.h +++ b/storage/innobase/include/ut0ut.h @@ -88,6 +88,11 @@ private: the YieldProcessor macro defined in WinNT.h. It is a CPU architecture- independent way by using YieldProcessor. */ # define UT_RELAX_CPU() YieldProcessor() +# elif defined(__powerpc__) +#include +# define UT_RELAX_CPU() do { \ + volatile lint volatile_var = __ppc_get_timebase(); \ + } while (0) # else # define UT_RELAX_CPU() ((void)0) /* avoid warning for an empty statement */ # endif diff --git a/storage/xtradb/include/ut0ut.h b/storage/xtradb/include/ut0ut.h index a14014dc618..328ccdf7430 100644 --- a/storage/xtradb/include/ut0ut.h +++ b/storage/xtradb/include/ut0ut.h @@ -85,6 +85,11 @@ private: the YieldProcessor macro defined in WinNT.h. It is a CPU architecture- independent way by using YieldProcessor. */ # define UT_RELAX_CPU() YieldProcessor() +# elif defined(__powerpc__) +#include +# define UT_RELAX_CPU() do { \ + volatile lint volatile_var = __ppc_get_timebase(); \ + } while (0) # else # define UT_RELAX_CPU() ((void)0) /* avoid warning for an empty statement */ # endif