Items that are part of net ties (pads and copper shapes that connect to
them) should allow connections from any net in the tie. This prevents
clearance errors from being generated for matched nets
Fixes https://gitlab.com/kicad/code/kicad/-/issues/14008
If two nets are joined by a global power pin but both have global labels
that override the net name, we still want them to be merged. This
checks for all net names in the drivers when looking for subgraph
merging candidates
Fixes https://gitlab.com/kicad/code/kicad/-/issues/18092
There was a motion towards fill solid/none around
2020 (c.f. b31e97cfed),
but it was only for PCB_SHAPE.
Use yes/no universally (solid/none parsing the same way
as currently). In future if there are other fill modes
for these shapes, they can use the same pattern as ZONEs
do now: (fill yes) (hatch etc ....) or similar.
Relates-To: https://gitlab.com/kicad/code/kicad/-/issues/15232
When zone kisses happen from different polygons, we need to be careful
not to use the different polygons for ear comparisons or prev/next
pointers
Fixes https://gitlab.com/kicad/code/kicad/-/issues/18654
- Moves functionality to FOOTPRINT class from BOARD_ITEM
- Renames DRC property from ComponentClass to Component_Class
- Adds DRC checks QA for A.Component_Class and a.hasComponentClass('x')
CHANGED: PCB file format now supports saving/loading complex padstacks
CHANGED: PTH pads are now rendered per copper layer in the copper color;
the PTH pad color is no longer used.
ADDED: support for importing complex pad stacks from Altium PCBs
Enforce padstack-aware access to pad properties across KiCad
Fixes https://gitlab.com/kicad/code/kicad/-/issues/8182
- Adds Component Class field to SCH_DIRECTIVE_LABEL
- Adds SCH_SYMBOLs to SCH_RULE_AREA item lists
- SCH_SYMBOLs resolve Component Class directives
- Netlist exporter / importer handles Component Class names
- Adds DRC expressions and functions
- Adds QA check for component class netlist export
F_Cu = 0
B_Cu = 2
Remaining internal copper layers are even and incrementing
Non-copper layers are odd and incrementing.
This means that we can no longer do things like:
for( PCB_LAYER_ID layer = F_Cu; layer <= B_Cu; ++layer)
Instead, we have the class LAYER_RANGE:
for( PCB_LAYER_ID layer : LAYER_RANGE( F_Cu, B_Cu) )
Similarly, gt/lt tests should not refer to the integer value of the
layer. We have functions such as IsCopperLayer to test whether a layer
is copper or not.
When using the connectivity RTree, the third dimension is layer, so we
provide B_Cu with the special INT_MAX value, ensuring that elements
between F_Cu and B_Cu will be identified. There is a new, special
function GetBoardLayer() for interfacing with CN_ITEMS
Similarly, PNS layers remain unchanged and sequential. A set of
interface functions is provided to map PNS layers to Board layers and
back. This allows the PNS_LAYER_RANGE to function as expected
Enables DRC to calculate skew based on new arguments to skew
constraint DRC clauses:
Using (group_matched): calculate skew across all matching nets
Using (within_diff_pairs): calculate skew within every diff pair
found within the matching nets
Additionally fixes DRC skew calculation to calculate skew relative
to the longest net in the skew check set (in line with PNS meander
placer calculations).
Sometimes we don't get the data elements in order. Use the stream name
to ensure we have the correct model.
Also give the parser a bit more memory to work with, avoiding unneeded
resizes
Power symbols are implicit labels in KiCad, so we should check for their
caps difference against other power symbols as well as against other
labels
Fixes https://gitlab.com/kicad/code/kicad/-/issues/16897
Previously, fills could end up just barely touching, leading to DRC
errors even if there was enough room to fill the remaining space. This
was due to how we shrink/expand the zones to remove small features. By
adding a zero-width line between points that should be connected, we
expand back to the correct width.
Fixes https://gitlab.com/kicad/code/kicad/-/issues/14130
The previous commit merged pads with copper areas. This was appealing
but broke when the pad and the area were meant to have different
size/shape technical layers. Small pads = Small paste. Instead, we do
not merge the pads but we assign them to have the appropriate nets in
KiCad, allowing the same effective result but keeping the technical
layers correct
Add direct handling of quadratic beziers to save compute time and number
of points. Update cubic interpolation to reduce number of points
generated for a given smoothness
Cache data on open and used cached data to avoid multiple re-calcs
Remove minimum line length and number of segments and replace with
standard max error level. Allows us to specify the tolerance of bezier
interpolation
Includes:
- Fix GAL to draw closed polygons in eeschema
- Add functionality to eeschema to draw arbitary polygons
- Update polygon item previews to have customisable edge colour
- Add new SCH_RULE_AREA class, derived from a poly SCH_SHAPE
- Add SCH_RULE_AREA to paint and plot methods
- Add new rule area color preference to themes
The schematic net names are fully unique but if we have multiple pads
that are mapped to a NC pin, they need to have unique net names so that
they do not get connected to each other in the ratsnest. This breaks
the schematic parity check as we have modified the netname for some
pads. To work around this, we first maintain the zero-th net without
suffix and then add an additional check in DRC to ensure that we allow
unconnected nets as long as the share a common prefix with the schematic
netname.
The connectivity routine would consider symbols, overwriting unused
subgraphs for pins that were not in the change list. This is resolved
by updating the full connectivity to only use pins in the graph since
symbols are not connected independently.
In the process of adding QA tests for this change, additional issues
with the schematic QA were discovered. Specifically, we were not
properly setting the root sheet UUID. This was partially masked by a
const_cast setting of the RefDes in sch_symbol when called the RefDes
getter. This exposed the fact that our QA ERC numbers did not match the
schematic editor stand alone ERC numbers. So the test value for one
check needed to be updated
Fixes https://gitlab.com/kicad/code/kicad/-/issues/17528
Polygon intersections happen against the original outline, not against
the currently remaining polygon. This avoids pathalogical cases
Adds new simplification system to avoid duplicated points
Adds new edge-splitting algorithm to provide additional fall-back
Verifies that polygon cuts do not swap holes for outlines (negative
area)
Fixes https://gitlab.com/kicad/code/kicad/-/issues/17559
JamesJCode
Seth Hillbrand
Dhineshkumar S
Jon Evans
John Beard
Daniel Treffenstädt
Jan Wichmann
Wayne Stambaugh
Tomasz Wlostowski
CraftedNightmare
Jeff Young
Alex Shvartzkop