NETCLASSes are stored as shared pointers. We lose the reference as soon
as the pointer count decrements to 0, which can happen immediately when
the shared pointer is returned.
ADDED Eeschema-specific netclass settings including wire and bus
thickness, color, and line style.
Netclasses override individual wire & bus colors and line styles.
If that proves an issue we might look at something more sophisticated
with inheritance.
Fixes https://gitlab.com/kicad/code/kicad/issues/4581
Various architecture upgrades to support this.
Creating a BOARD now requires a valid PROJECT, which caused
some (mostly transparent) changes to the Python API internals.
ADDED: Project local settings file
CHANGED: Board design settings are no longer stored in PCB file
CHANGED: Net classes are no longer stored in PCB file
CHANGED: Importing board settings now reads boards, not just projects
Fixes https://gitlab.com/kicad/code/kicad/-/issues/2578
Fixes https://gitlab.com/kicad/code/kicad/-/issues/4070
*) Extend SWIG support deeper into the BOARD class.
*) Move swig *.i files into a directory identified for SWIG, in preparation
for a parallel universe involving Phoenix's SIP.
*) Move swig files which will be common to both eeschema and pcbnew into
common/swig.
*) Sketch out a "common" python module, and plan on dovetailing that into a
libkicad_shared.{dll,so}
*) Add common/swig/ki_exceptions.i and define a macro HANDLE_EXCEPTIONS()
which is to be applied to any function which needs C++ to python
exception translation.
*) Move the test for SWIG tool into top level CMakeLists.txt file for use
in all python modules beyond pcbnew, i.e. eeschema and common.
*) Add SWIG_MODULE_pcbnew_EXTRA_DEPS which generates a better Makefile, one
which rebuilds the swig generated *.cxx file when one of its dependencies
change.
*) Re-architect the board.i file so that it can be split into multiple *.i
files easily.
*) Make some KIWAY from python progress, in preparation for Modular KiCad
phase III.
* Switched hashtables.h over to std::undordered_map from boost version.
* Added new macros DECL_VEC_FOR_SWIG() and DECL_MAP_FOR_SWIG() in macros.h.
These along with future DECL_HASH_FOR_SWIG() unify the declaration to swig
and C++ so that the resultant type name is common in both languages, and
the types AGREE.
* Fixed swigging of NETINFO_ITEM and NETINFO_LIST via magic.
* Newly exposed (python wrapped) are: D_PADS, TRACKS (was TRACK_PTRS),
NETNAME_MAP, NETCODE_MAP, wxString (without constructor purposely, read
comment in wx.i), MARKERS, ZONE_CONTAINERS, NETCLASSPTR, KICAD_T types.
* std::vector<SOMETHING*> tends to end up named SOMETHINGS in C++ and python.
Having the name consistent between like types is helpful, and between
languages. std::map<> ends up as SOMETHING_MAP.
* NETINFO_LIST::m_netNames and NETINFO_LIST::m_netCodes are now std::map
instead of hashtables, because swig does not yet support std::unordered_map.
* You can now get to any netclass or net info. NETNAMES_MAP and NETCODES_MAP
are traversable basically the same as a python dictionary using a python
string (not wsString) as the key! The wxString typemap converts python
string to wxString before the lookup happens. Iteration also works.
legacy plugin: better compatibility with old brd files (current track width and current vias size, stored in SETUP section, were not read from file and incorrectly set)
Most of the changes are just adding GetDesignSettings() before every occurence of m_NetClasses.
More complex changes:
class_netclass.cpp - NETCLASS does not store the pointer to the parent BOARD anymore. Added function SetParams( BOARD_DESIGN_SETTINGS& ).
class_netclass.h - Removed GetTrackMinWidth(), GetViaMinDiameter(), GetViaMinDrill(), GetuViaMinDiameter(), GetuViaMinDrill() as they were refering to BOARD_DESIGN_SETTINGS anyway (they are not net class specific).
kicad_plugin.cpp - filters out empty nets (that are anyway not saved) when storing net class information. Previously it was done in NETCLASS::Format() function.
* Add s-expression Format() function to all objects derived from
BOARD_ITEM.
* Add s-expression Format() function to base objects as required.
* Add functions to convert coordinates from base internal units
(nanometers) to millimeter string for writing to s-expression
file.
* Add temporary dummy conversion functions to prevent link errors
until schematic and board object and action code can be separated
into DSO/DLL.
* Add CMake build option to build Pcbnew with nanometer internal
units.
* Correct all user strings and comments for the correct capitalization of
application names according to JP. They are KiCad, Pcbnew, CvPcb,
Eeschema, and GerbView.
* Add a note the the user interface policy about the correct capitalization.
* All header files used to create the PCB common library now compile as
stand alone code. This prevents the need to define them in a specific
order to make source code compile properly. It should also now be
possible to relocate the source code to build the common PCB library
to a separate folder.
* Remove base screen methods from draw frame object and correct current
screen methods in derived objects.
* Move restore old wires function code into schematic screen object.
* Make add junction method use current screen position instead of store
position.
* Move poly line ghosting function into the delete current segment method
as that was the only place is was being used.
* Add method to base schematic object of testing if object has a label
that can be incremented.
* Simplified the schematic hierarchy traversing code.
* PCBNew Doxygen warning fixes.
Seth Hillbrand
Wayne Stambaugh
Marek Roszko
Tomasz Wlostowski
Jeff Young
Jon Evans
jean-pierre charras
Camille
Marvin Schmidt
Maciej Suminski
Kristoffer Ödmark
Simon Richter
Dick Hollenbeck
Miguel Angel Ajo
Wayne Stambaugh
Vladimir Ur
Marco Mattila
charras