78 Commits (662f6c7d83d7c41a395e4050c96497c99bb637f3)

Author SHA1 Message Date
Jeff Young 86938aa425 Read, write and process the board-wide Allow soldermask bridges in FPs. 3 years ago
Jeff Young a9536b5de9 CHANGED netclass assignments now done via canvas or via patterns. 3 years ago
Seth Hillbrand a9a5136c1c Always allow blind/buried/micro vias 3 years ago
Seth Hillbrand 3081023b5e ADDED: Minimum copper connection width DRC check 3 years ago
Jeff Young 3deaf902bb Retire the V5 zone fill algorithm. 4 years ago
jean-pierre charras 1b42152ba0 Teardrops: store parameters in BOARD_DESIGN_SETTINGS. 4 years ago
Marek Roszko 347e03363a Convert wxPoint/wxSize starting from EDA_RECT usages 4 years ago
Jeff Young dabc75bee8 Source 3D dimensions from board stackup. 4 years ago
Jeff Young ef10b36948 Add mask-to-copper clearance parameter and rename mask margin. 4 years ago
Jeff Young a1e3f2b188 Starved thermals DRC checking. 4 years ago
Jeff Young 2001d08186 Add DRC tests for text height and text thickness. 4 years ago
Mike Williams 956ac871c3 PCB Editor: changes to track width overrides starting track width 4 years ago
Jeff Young 1f9e75f676 Pad with hole same size or larger than pad isn't flashed. 4 years ago
Jon Evans 75d75799f7 Move to getters/setters for aux and grid origin 4 years ago
Jeff Young 81fc710a5d Use consistent terminology. 4 years ago
Marek Roszko 10e60acf34 Clean up including of board_design_settings.h 5 years ago
Jon Evans bc6b9b527a Allow stackup height to be excluded from length calculations 5 years ago
Wayne Stambaugh 2ae264751f Rename class_board_stackup.{h|cpp} to board_stackup.{h|cpp}. 5 years ago
Jeff Young 3e9eb3c8ac More complete fix for crasher JP found. 5 years ago
Jon Evans 68f958145d Gracefully handle lack of diff pair settings 5 years ago
Dominik Wernberger ac94d72d2d Add more const specifiers 5 years ago
Wayne Stambaugh bf00ebee3b Header clean up round 1. 5 years ago
Jeff Young 3b35bfc0a5 Don't write out synthetic severities (they're headings). 5 years ago
Jeff Young e09271ca0e Fixes for hole clearance and hole-to-hole tests. 5 years ago
jean-pierre charras a431fd99ca Fix crash when converting a Eagle board to a Kicad board. 5 years ago
Jeff Young 61bca4aaa4 A bit of "module" erradication, nameing conventions, and formatting. 5 years ago
Jeff Young f5443de7f9 D_PAD -> PAD. 5 years ago
Jeff Young 84dd5108ba Remove some "class_" prefixes from files. 5 years ago
Jeff Young f7333ad64a Update some classnames including archaic zone names. 5 years ago
Jeff Young 32dffd27ab Add silk clearance to board setup constraints. 5 years ago
Jeff Young 614d452f12 Resolve trackwidth[0]/viasize[0] to be the netclass values. 5 years ago
Jeff Young 04c4012ee6 Make track/via sizes UI more predictable and compatible with DRC. 5 years ago
Jon Evans 728c207105 Deduplicate settings migration handling 5 years ago
Jeff Young f340636f70 When knocking out higher-priority zone use fill, not outline. 5 years ago
Jeff Young e2e229da96 Finish exorcising the old DRC system. 5 years ago
Jon Evans 3940e20fcb Expose extension offset and zero suppression settings 5 years ago
Jon Evans 0e9997d9ca Add new dimension features to board design defaults 5 years ago
Jon Evans ae7877c6cb Migrate dimension precision 5 years ago
Jon Evans b11e315d10 Refactor DIMENSION to hide internal details; add some new properties 5 years ago
Jeff Young d1006138fd ADDED holeWallPlatingThickness to AdvancedCfg. 5 years ago
Jeff Young 38e9217d54 Consolidate all DRC epsilon/threshold values to a single advancedCfg setting. 5 years ago
Jeff Young 305abb210f Add a mode to allow zone smoothing to produce external fillets. 5 years ago
jean-pierre charras df4226f896 Settings management: try to fix full filename issues when using non ASCII7 chars. 5 years ago
Jeff Young 095937563b Hook libeval compiler up to rule parser 5 years ago
Jeff Young 741481591e NetClass settings for Eeschema. 5 years ago
Jon Evans db4502e2ae Add copy ctor for BOARD_DESIGN_SETTINGS 5 years ago
Jon Evans a9e97848dd Fix use after free on BOARD_DESIGN_SETTINGS 5 years ago
Jon Evans c0aa6965de Migrate PcbNew project settings to new framework 6 years ago
jean-pierre charras 27c80e8a2e Solder mask clearance default value: set default to 0, taking advice from 6 years ago
Jeff Young f4d8c30f9a Tighten DRC epsilon value until we decide what to do about it. 6 years ago