Implement bracket notation for stacked pins ([1,2,3], [1-4], [1,3,5-7]).
Automatic net naming proceeds based on the smallest logical pin number
in stacked groups.
Provide explode/reform commands in symbol editor for conversion.
Supports arbitrary ranges including BGA alphanum ranges like
[AA1-AA3,CD14-CD22]
Adds some additional QA and trace logging
Fixes https://gitlab.com/kicad/code/kicad/-/issues/2004
If you have a pin with a label containing the letters "GND" in it and it
is not connected to a net with a label also containing "GND" AND there
is another pin on your symbol that _is_ connected to a net containing
"GND", then there is a likelihood that you have accidentally mixed up
your connections to the GND pin
If global or local labels are floating -> error
If global or local labels are only connected to one pin -> warning
Rather than forcing two different errors depending on whether the label
is local or global
Support explicit jumper symbols, defined either by a
flag that all pins with the same number are connected,
or by explicit groups of jumpered pins
Fixes https://gitlab.com/kicad/code/kicad/-/issues/2558
If two nets are joined by a global power pin but both have global labels
that override the net name, we still want them to be merged. This
checks for all net names in the drivers when looking for subgraph
merging candidates
Fixes https://gitlab.com/kicad/code/kicad/-/issues/18092
- Adds Component Class field to SCH_DIRECTIVE_LABEL
- Adds SCH_SYMBOLs to SCH_RULE_AREA item lists
- SCH_SYMBOLs resolve Component Class directives
- Netlist exporter / importer handles Component Class names
- Adds DRC expressions and functions
- Adds QA check for component class netlist export
Power symbols are implicit labels in KiCad, so we should check for their
caps difference against other power symbols as well as against other
labels
Fixes https://gitlab.com/kicad/code/kicad/-/issues/16897
Includes:
- Fix GAL to draw closed polygons in eeschema
- Add functionality to eeschema to draw arbitary polygons
- Update polygon item previews to have customisable edge colour
- Add new SCH_RULE_AREA class, derived from a poly SCH_SHAPE
- Add SCH_RULE_AREA to paint and plot methods
- Add new rule area color preference to themes
The connectivity routine would consider symbols, overwriting unused
subgraphs for pins that were not in the change list. This is resolved
by updating the full connectivity to only use pins in the graph since
symbols are not connected independently.
In the process of adding QA tests for this change, additional issues
with the schematic QA were discovered. Specifically, we were not
properly setting the root sheet UUID. This was partially masked by a
const_cast setting of the RefDes in sch_symbol when called the RefDes
getter. This exposed the fact that our QA ERC numbers did not match the
schematic editor stand alone ERC numbers. So the test value for one
check needed to be updated
Fixes https://gitlab.com/kicad/code/kicad/-/issues/17528
We have a break somewhere in the connectivity that doesn't fully process
connections but the current code seems to catch these by forcing a
top-down & bottom-up calculation
Fixes https://gitlab.com/kicad/code/kicad/-/issues/14818
Aliases in bus resolution were being resolved without a path, making
them effectively global nets. This applies the corrected path to the
bus members and adds a QA to catch this error
The propagation is currently (maybe not needed) limited to the global
name that is the source of the change. We also need to propagate the
global name that is changed in case the global is set in a tree leaf and
not the root
Fixes https://gitlab.com/kicad/code/kicad/issues/14657
Previously, bus elements that were not instantiated as individual nets
could not connect to each other. This caused issues for complex
schematics where busses needed to connect to other busses with elements
that resolved to the same net names. Functionally, this means mixing
bus elements, which we will replace with first-class elements in version
8 but currently can only be accomplished either by using bus aliases and
this patch or by individually instantiating each bus element as a
local label
Fixes https://gitlab.com/kicad/code/kicad/issues/14300
Fixes#12580
Additionally does not export no_connect netlist annotation on pins
which are both connected to another pin and a NC item, unless all
connected pins are stacked at the symbol level.
Adds testing of pin types to netlist QA unit tests.
Fixes#10926
Contains the following changes:
- Adds a new ERC_SCH_PIN_CONTEXT class which is used to provide deterministic
comparison between items causing ERC violations (e.g. pins) when associated
with a SCH_SHEET_PATH context.
- Adds association of SCH_SHEET_PATHs for ERC_ITEMs and the sub-schematic items
which caused an ERC violation. This allows correct display of markers on the
sheets of interest only, and allows correct naming resolution and cross-probing
from the ERC dialog.
- Adds a new ERC_TREE_MODEL class, derived from RC_TREE_MODEL, which correctly
resolves component references across heirarchical sheets using the associated
SCH_SHEET_PATHs. This allows sheet-specific component references to be displayed
correctly in the ERC results tree.
- Updates SCH_MARKER to only draw sheet-specific markers on the sheet causing
an ERC violation.
- Increments the schematic file version.
- When loading a schematic with legacy ERC exclusions, discards those of type
ERCE_PIN_TO_PIN_WARNING, ERCE_PIN_TO_PIN_ERROR, ERCE_HIERACHICAL_LABEL, and
ERCE_DIFFERENT_UNIT_NET as there is no safe way to automatically infer the
information which is now stored with these exclusions (sheet paths for error
location and related items). Requiring users to (once) re-add exclusions is
preferable to silently incorrectly matching new ERC issues to legacy exclusions.
Seth Hillbrand
Mike Williams
Jon Evans
JamesJCode
Daniel Treffenstädt
Jan Wichmann
Wayne Stambaugh
CraftedNightmare
Jeff Young
Ian McInerney
Roberto Fernandez Bautista
Marek Roszko
jean-pierre charras