From e2e229da96ee52866e823d56f9f75b5f01780e1f Mon Sep 17 00:00:00 2001 From: Jeff Young Date: Tue, 15 Sep 2020 20:13:45 +0100 Subject: [PATCH] Finish exorcising the old DRC system. This moves the various BOARD_ITEM calls to the new system, and make the DRC_ENGINE long-lived so that it can field those queries. --- common/CMakeLists.txt | 2 + include/board_design_settings.h | 8 +- pcbnew/CMakeLists.txt | 3 - pcbnew/board_connected_item.cpp | 77 ++----------- pcbnew/board_connected_item.h | 2 +- pcbnew/board_design_settings.cpp | 24 ++--- pcbnew/class_track.cpp | 76 ++++++------- pcbnew/class_zone.cpp | 77 ------------- pcbnew/class_zone.h | 9 -- pcbnew/cleanup_item.h | 3 +- pcbnew/dialogs/dialog_board_setup.cpp | 1 - pcbnew/dialogs/dialog_cleanup_graphics.cpp | 1 + pcbnew/dialogs/dialog_drc.h | 1 - pcbnew/dialogs/panel_setup_rules.cpp | 11 +- pcbnew/drc/drc.cpp | 101 ------------------ pcbnew/drc/drc.h | 71 ------------ pcbnew/drc/drc_engine.cpp | 66 ++++++------ pcbnew/drc/drc_engine.h | 9 +- pcbnew/drc/drc_item.cpp | 44 -------- pcbnew/drc/drc_item.h | 7 -- pcbnew/drc/drc_rule.cpp | 48 --------- pcbnew/drc/drc_test_provider_annulus.cpp | 1 - pcbnew/drc/drc_test_provider_connectivity.cpp | 1 - .../drc_test_provider_copper_clearance.cpp | 4 +- .../drc_test_provider_courtyard_clearance.cpp | 1 - pcbnew/drc/drc_test_provider_disallow.cpp | 1 - .../drc/drc_test_provider_edge_clearance.cpp | 1 - .../drc/drc_test_provider_hole_clearance.cpp | 2 +- pcbnew/drc/drc_test_provider_hole_size.cpp | 2 +- pcbnew/drc/drc_test_provider_lvs.cpp | 1 - pcbnew/drc/drc_test_provider_misc.cpp | 1 - pcbnew/drc/drc_test_provider_track_width.cpp | 1 - pcbnew/drc/drc_test_provider_via_diameter.cpp | 1 - pcbnew/footprint_editor_settings.cpp | 1 - pcbnew/menubar_pcb_editor.cpp | 1 - pcbnew/pcb_base_edit_frame.cpp | 4 + pcbnew/pcb_edit_frame.cpp | 4 - pcbnew/tools/drc_tool.cpp | 27 ++--- pcbnew/tools/drc_tool.h | 5 +- pcbnew/tools/pcb_inspection_tool.cpp | 5 - pcbnew/zones_by_polygon.cpp | 1 - .../drc_test_provider_silk_to_pad.cpp | 5 +- qa/pcbnew_utils/board_construction_utils.cpp | 2 - 43 files changed, 135 insertions(+), 578 deletions(-) delete mode 100644 pcbnew/drc/drc.cpp delete mode 100644 pcbnew/drc/drc.h diff --git a/common/CMakeLists.txt b/common/CMakeLists.txt index d9972deb32..6920d554b9 100644 --- a/common/CMakeLists.txt +++ b/common/CMakeLists.txt @@ -509,9 +509,11 @@ set( PCB_COMMON_SRCS ${CMAKE_SOURCE_DIR}/pcbnew/connectivity/connectivity_items.cpp ${CMAKE_SOURCE_DIR}/pcbnew/connectivity/connectivity_data.cpp ${CMAKE_SOURCE_DIR}/pcbnew/convert_drawsegment_list_to_polygon.cpp + ${CMAKE_SOURCE_DIR}/pcbnew/drc/drc_engine.cpp ${CMAKE_SOURCE_DIR}/pcbnew/drc/drc_item.cpp ${CMAKE_SOURCE_DIR}/pcbnew/drc/drc_rule.cpp ${CMAKE_SOURCE_DIR}/pcbnew/drc/drc_rule_condition.cpp + ${CMAKE_SOURCE_DIR}/pcbnew/drc/drc_rule_parser.cpp ${CMAKE_SOURCE_DIR}/pcbnew/eagle_plugin.cpp ${CMAKE_SOURCE_DIR}/pcbnew/footprint_editor_settings.cpp ${CMAKE_SOURCE_DIR}/pcbnew/gpcb_plugin.cpp diff --git a/include/board_design_settings.h b/include/board_design_settings.h index a2c82f7a13..dafc8c70c7 100644 --- a/include/board_design_settings.h +++ b/include/board_design_settings.h @@ -29,7 +29,7 @@ #include #include #include -#include +#include #include #include #include @@ -240,9 +240,9 @@ public: int m_CopperEdgeClearance; int m_HoleToHoleMin; // Min width of peninsula between two drilled holes - std::vector m_DRCRules; - std::map< int, int > m_DRCSeverities; // Map from DRCErrorCode to SEVERITY - std::set m_DrcExclusions; + std::shared_ptr m_DRCEngine; + std::map m_DRCSeverities; // Map from DRCErrorCode to SEVERITY + std::set m_DrcExclusions; // Option to handle filled polygons in zones: // the "legacy" option is using thick outlines around filled polygons: give the best shape diff --git a/pcbnew/CMakeLists.txt b/pcbnew/CMakeLists.txt index 24c15da175..d4f38d71ca 100644 --- a/pcbnew/CMakeLists.txt +++ b/pcbnew/CMakeLists.txt @@ -232,9 +232,6 @@ set( PCBNEW_MICROWAVE_SRCS ) set( PCBNEW_DRC_SRCS - drc/drc.cpp - drc/drc_engine.cpp - drc/drc_rule_parser.cpp drc/drc_test_provider.cpp drc/drc_test_provider_annulus.cpp drc/drc_test_provider_clearance_base.cpp diff --git a/pcbnew/board_connected_item.cpp b/pcbnew/board_connected_item.cpp index ec4f5e79ff..9af92b6d24 100644 --- a/pcbnew/board_connected_item.cpp +++ b/pcbnew/board_connected_item.cpp @@ -27,6 +27,7 @@ #include #include #include +#include using namespace std::placeholders; @@ -81,82 +82,26 @@ NETCLASS* BOARD_CONNECTED_ITEM::GetEffectiveNetclass() const * LEVEL 3: Accumulated local settings, netclass settings, & board design settings */ int BOARD_CONNECTED_ITEM::GetClearance( PCB_LAYER_ID aLayer, BOARD_ITEM* aItem, - wxString* aSource, REPORTER* aReporter ) const + wxString* aSource ) const { - BOARD* board = GetBoard(); - int clearance = 0; - wxString source; - wxString* localSource = aSource ? &source : nullptr; - BOARD_CONNECTED_ITEM* second = dynamic_cast( aItem ); - // No clearance if "this" is not (yet) linked to a board therefore no available netclass - if( !board ) - return clearance; - - // LEVEL 1: local overrides (pad, footprint, etc.) - // - if( GetLocalClearanceOverrides( nullptr ) > clearance ) - clearance = GetLocalClearanceOverrides( localSource ); - - if( second && second->GetLocalClearanceOverrides( nullptr ) > clearance ) - clearance = second->GetLocalClearanceOverrides( localSource ); - - if( clearance ) - { - if( aSource ) - *aSource = *localSource; - - return clearance; - } - - // LEVEL 2: Rules - // - const DRC_CONSTRAINT* constraint = GetConstraint( this, aItem, DRC_CONSTRAINT_TYPE_CLEARANCE, - aLayer, aSource ); - - if( constraint ) - { - if( aSource ) - *aSource = wxString::Format( _( "'%s' rule" ), *aSource ); + if( !GetBoard() ) + return 0; - return constraint->m_Value.Min(); - } + std::shared_ptr drcEngine = GetBoard()->GetDesignSettings().m_DRCEngine; - // LEVEL 3: Accumulated local settings, netclass settings, & board design settings - // - BOARD_DESIGN_SETTINGS& bds = board->GetDesignSettings(); - NETCLASS* netclass = GetEffectiveNetclass(); - NETCLASS* secondNetclass = second ? second->GetEffectiveNetclass() : nullptr; + DRC_CONSTRAINT constraint = drcEngine->EvalRulesForItems( DRC_CONSTRAINT_TYPE_CLEARANCE, + this, aItem, aLayer ); - if( bds.m_MinClearance > clearance ) + if( constraint.Value().HasMin() ) { if( aSource ) - *aSource = _( "board minimum" ); + *aSource = constraint.GetName(); - clearance = bds.m_MinClearance; + return constraint.Value().Min(); } - if( netclass && netclass->GetClearance() > clearance ) - clearance = netclass->GetClearance( aSource ); - - if( secondNetclass && secondNetclass->GetClearance() > clearance ) - clearance = secondNetclass->GetClearance( aSource ); - - if( aItem && aItem->GetLayer() == Edge_Cuts && bds.m_CopperEdgeClearance > clearance ) - { - if( aSource ) - *aSource = _( "board edge" ); - - clearance = bds.m_CopperEdgeClearance; - } - - if( GetLocalClearance( nullptr ) > clearance ) - clearance = GetLocalClearance( aSource ); - - if( second && second->GetLocalClearance( nullptr ) > clearance ) - clearance = second->GetLocalClearance( aSource ); - - return clearance; + return 0; } diff --git a/pcbnew/board_connected_item.h b/pcbnew/board_connected_item.h index b9433212c1..c6f57faf75 100644 --- a/pcbnew/board_connected_item.h +++ b/pcbnew/board_connected_item.h @@ -168,7 +168,7 @@ public: * @return int - the clearance in internal units. */ virtual int GetClearance( PCB_LAYER_ID aLayer, BOARD_ITEM* aItem = nullptr, - wxString* aSource = nullptr, REPORTER* aReporter = nullptr ) const; + wxString* aSource = nullptr ) const; /** * Function GetLocalClearanceOverrides diff --git a/pcbnew/board_design_settings.cpp b/pcbnew/board_design_settings.cpp index b50b85b23e..939e655e78 100644 --- a/pcbnew/board_design_settings.cpp +++ b/pcbnew/board_design_settings.cpp @@ -27,11 +27,9 @@ #include #include #include -//#include #include -#include -//#include -#include +#include +#include #include #include #include @@ -626,7 +624,6 @@ void BOARD_DESIGN_SETTINGS::initFromOther( const BOARD_DESIGN_SETTINGS& aOther ) m_TrackWidthList = aOther.m_TrackWidthList; m_ViasDimensionsList = aOther.m_ViasDimensionsList; m_DiffPairDimensionsList = aOther.m_DiffPairDimensionsList; - m_DRCRules = aOther.m_DRCRules; m_MicroViasAllowed = aOther.m_MicroViasAllowed; m_BlindBuriedViaAllowed = aOther.m_BlindBuriedViaAllowed; m_CurrentViaType = aOther.m_CurrentViaType; @@ -935,21 +932,12 @@ bool BOARD_DESIGN_SETTINGS::SetCurrentNetClass( const wxString& aNetClassName ) int BOARD_DESIGN_SETTINGS::GetBiggestClearanceValue() { - int clearance = GetDefault()->GetClearance(); - - for( const std::pair& netclass : GetNetClasses().NetClasses() ) - clearance = std::max( clearance, netclass.second->GetClearance() ); + DRC_CONSTRAINT constraint; - for( const DRC_RULE* rule : m_DRCRules ) - { - for( const DRC_CONSTRAINT& constraint : rule->m_Constraints ) - { - if( constraint.m_Type == DRC_CONSTRAINT_TYPE_CLEARANCE ) - clearance = std::max( clearance, constraint.m_Value.Min() ); - } - } + m_DRCEngine->QueryWorstConstraint( DRC_CONSTRAINT_TYPE_CLEARANCE, constraint, + DRCCQ_LARGEST_MINIMUM ); - return clearance; + return constraint.Value().HasMin() ? constraint.Value().Min() : 0; } diff --git a/pcbnew/class_track.cpp b/pcbnew/class_track.cpp index addbf96916..64298f2905 100644 --- a/pcbnew/class_track.cpp +++ b/pcbnew/class_track.cpp @@ -38,6 +38,7 @@ #include #include #include +#include TRACK::TRACK( BOARD_ITEM* aParent, KICAD_T idtype ) : BOARD_CONNECTED_ITEM( aParent, idtype ) @@ -124,52 +125,41 @@ int TRACK::GetLocalClearance( wxString* aSource ) const } -/* - * Width constraints exist in a hiearchy. If a given level is specified then the remaining - * levels are NOT consulted. - * - * LEVEL 1: (highest priority) local overrides (not currently implemented.) - * LEVEL 2: Rules - * LEVEL 3: Accumulated local settings, netclass settings, & board design settings - */ void TRACK::GetWidthConstraints( int* aMin, int* aMax, wxString* aSource ) const { - // LEVEL 1: local overrides - // - // Not currently implemented + // No constraints if "this" is not (yet) linked to a board + if( !GetBoard() ) + { + *aMin = 0; + *aMax = INT_MAX; + return; + } + + std::shared_ptr drcEngine = GetBoard()->GetDesignSettings().m_DRCEngine; - // LEVEL 2: Rules - const DRC_CONSTRAINT* constraint = GetConstraint( this, nullptr, - DRC_CONSTRAINT_TYPE_TRACK_WIDTH, - m_Layer, aSource ); + DRC_CONSTRAINT constraint = drcEngine->EvalRulesForItems( DRC_CONSTRAINT_TYPE_TRACK_WIDTH, + this, nullptr, GetLayer() ); - if( constraint ) + if( constraint.Value().HasMin() || constraint.Value().HasMax() ) { - *aMin = constraint->m_Value.Min(); - *aMax = constraint->m_Value.Max(); + if( constraint.Value().HasMin() ) + *aMin = constraint.Value().Min(); - if( aSource ) - *aSource = wxString::Format( _( "'%s' rule" ), *aSource ); + if( constraint.Value().HasMax() ) + *aMax = constraint.Value().Max(); - return; + if( aSource ) + *aSource = constraint.GetName(); } - - // LEVEL 3: Netclasses & board design settings - // - // Note that local settings aren't currently implemented, and netclasses don't contain a - // minimum width (only a default width), so only the board design settings are relevant - // here. - // - *aMin = GetBoard()->GetDesignSettings().m_TrackMinWidth; - *aMax = INT_MAX / 2; - - if( aSource ) - *aSource = _( "board minimum" ); } int VIA::GetMinAnnulus( PCB_LAYER_ID aLayer, wxString* aSource ) const { + // No constraints if "this" is not (yet) linked to a board + if( !GetBoard() ) + return 0; + if( !IsPadOnLayer( aLayer ) ) { if( aSource ) @@ -178,24 +168,20 @@ int VIA::GetMinAnnulus( PCB_LAYER_ID aLayer, wxString* aSource ) const return 0; } - const DRC_CONSTRAINT* constraint = GetConstraint( this, nullptr, - DRC_CONSTRAINT_TYPE_ANNULUS_WIDTH, - aLayer, aSource ); + std::shared_ptr drcEngine = GetBoard()->GetDesignSettings().m_DRCEngine; - if( constraint ) - { - if( aSource ) - *aSource = wxString::Format( _( "'%s' rule" ), *aSource ); + DRC_CONSTRAINT constraint = drcEngine->EvalRulesForItems( DRC_CONSTRAINT_TYPE_ANNULUS_WIDTH, + this, nullptr, aLayer ); - return constraint->m_Value.Min(); - } - else + if( constraint.Value().HasMin() ) { if( aSource ) - *aSource = _( "board minimum" ); + *aSource = constraint.GetName(); - return GetBoard()->GetDesignSettings().m_ViasMinAnnulus; + return constraint.Value().Min(); } + + return 0; } diff --git a/pcbnew/class_zone.cpp b/pcbnew/class_zone.cpp index 1871797d11..571cf0f20f 100644 --- a/pcbnew/class_zone.cpp +++ b/pcbnew/class_zone.cpp @@ -353,83 +353,6 @@ int ZONE_CONTAINER::GetThermalReliefCopperBridge( D_PAD* aPad, wxString* aSource } -int ZONE_CONTAINER::GetKeepouts( PCB_LAYER_ID aLayer, std::map* aSources ) const -{ - wxString source; - int keepouts = 0; - - auto setFlag = [&]( int aFlag ) - { - keepouts |= aFlag; - - if( aSources ) - (*aSources)[ aFlag ] = source; - }; - - if( m_isKeepout ) - { - if( aSources ) - source = _( "zone properties" ); - - if( m_doNotAllowTracks ) - setFlag( DRC_DISALLOW_TRACKS ); - - if( m_doNotAllowVias ) - setFlag( DRC_DISALLOW_VIAS ); - - if( m_doNotAllowPads ) - setFlag( DRC_DISALLOW_PADS ); - - if( m_doNotAllowFootprints ) - setFlag( DRC_DISALLOW_FOOTPRINTS ); - - if( m_doNotAllowCopperPour ) - setFlag( DRC_DISALLOW_ZONES ); - } - - const DRC_CONSTRAINT* constraint = GetConstraint( this, nullptr, DRC_CONSTRAINT_TYPE_DISALLOW, - aLayer, &source ); - - if( constraint ) - { - if( aSources ) - source = wxString::Format( _( "'%s' rule" ), source ); - - if( ( constraint->m_DisallowFlags & DRC_DISALLOW_VIAS ) > 0 ) - setFlag( DRC_DISALLOW_VIAS ); - - if( ( constraint->m_DisallowFlags & DRC_DISALLOW_MICRO_VIAS ) > 0 ) - setFlag( DRC_DISALLOW_MICRO_VIAS ); - - if( ( constraint->m_DisallowFlags & DRC_DISALLOW_BB_VIAS ) > 0 ) - setFlag( DRC_DISALLOW_BB_VIAS ); - - if( ( constraint->m_DisallowFlags & DRC_DISALLOW_TRACKS ) > 0 ) - setFlag( DRC_DISALLOW_TRACKS ); - - if( ( constraint->m_DisallowFlags & DRC_DISALLOW_PADS ) > 0 ) - setFlag( DRC_DISALLOW_PADS ); - - if( ( constraint->m_DisallowFlags & DRC_DISALLOW_ZONES ) > 0 ) - setFlag( DRC_DISALLOW_ZONES ); - - if( ( constraint->m_DisallowFlags & DRC_DISALLOW_TEXTS ) > 0 ) - setFlag( DRC_DISALLOW_TEXTS ); - - if( ( constraint->m_DisallowFlags & DRC_DISALLOW_GRAPHICS ) > 0 ) - setFlag( DRC_DISALLOW_GRAPHICS ); - - if( ( constraint->m_DisallowFlags & DRC_DISALLOW_HOLES ) > 0 ) - setFlag( DRC_DISALLOW_HOLES ); - - if( ( constraint->m_DisallowFlags & DRC_DISALLOW_FOOTPRINTS ) > 0 ) - setFlag( DRC_DISALLOW_FOOTPRINTS ); - } - - return keepouts; -} - - void ZONE_CONTAINER::SetCornerRadius( unsigned int aRadius ) { if( m_cornerRadius != aRadius ) diff --git a/pcbnew/class_zone.h b/pcbnew/class_zone.h index 76515b7d5f..b3661d4a4a 100644 --- a/pcbnew/class_zone.h +++ b/pcbnew/class_zone.h @@ -714,15 +714,6 @@ public: bool GetDoNotAllowPads() const { return m_doNotAllowPads; } bool GetDoNotAllowFootprints() const { return m_doNotAllowFootprints; } - /** - * Return a bitset of flags for keepouts. Includes both those set via the GUI - * and those set via DRC rules. - * @aSources indicates the source ("zone properties" or rule name) of each - * flag. - * @return a bitset of DISALLOW_* flags. - */ - int GetKeepouts( PCB_LAYER_ID aLayer, std::map* aSources = nullptr ) const; - void SetIsKeepout( bool aEnable ) { m_isKeepout = aEnable; } void SetDoNotAllowCopperPour( bool aEnable ) { m_doNotAllowCopperPour = aEnable; } void SetDoNotAllowVias( bool aEnable ) { m_doNotAllowVias = aEnable; } diff --git a/pcbnew/cleanup_item.h b/pcbnew/cleanup_item.h index cf7b8a1ef3..bff66d06f7 100644 --- a/pcbnew/cleanup_item.h +++ b/pcbnew/cleanup_item.h @@ -24,8 +24,7 @@ #ifndef CLEANUP_ITEM_H #define CLEANUP_ITEM_H -#include -#include +#include class PCB_BASE_FRAME; diff --git a/pcbnew/dialogs/dialog_board_setup.cpp b/pcbnew/dialogs/dialog_board_setup.cpp index 879b8b046e..c628b77970 100644 --- a/pcbnew/dialogs/dialog_board_setup.cpp +++ b/pcbnew/dialogs/dialog_board_setup.cpp @@ -26,7 +26,6 @@ #include <../board_stackup_manager/panel_board_stackup.h> #include #include -#include #include #include #include diff --git a/pcbnew/dialogs/dialog_cleanup_graphics.cpp b/pcbnew/dialogs/dialog_cleanup_graphics.cpp index 8d58745c79..441cf352e1 100644 --- a/pcbnew/dialogs/dialog_cleanup_graphics.cpp +++ b/pcbnew/dialogs/dialog_cleanup_graphics.cpp @@ -26,6 +26,7 @@ #include #include #include +#include DIALOG_CLEANUP_GRAPHICS::DIALOG_CLEANUP_GRAPHICS( PCB_BASE_FRAME* aParent, bool isModEdit ) : diff --git a/pcbnew/dialogs/dialog_drc.h b/pcbnew/dialogs/dialog_drc.h index f839e6757a..a2c427715d 100644 --- a/pcbnew/dialogs/dialog_drc.h +++ b/pcbnew/dialogs/dialog_drc.h @@ -30,7 +30,6 @@ #include #include #include -#include #include #include #include diff --git a/pcbnew/dialogs/panel_setup_rules.cpp b/pcbnew/dialogs/panel_setup_rules.cpp index 50ca904863..db2ea822a1 100644 --- a/pcbnew/dialogs/panel_setup_rules.cpp +++ b/pcbnew/dialogs/panel_setup_rules.cpp @@ -25,15 +25,16 @@ #include #include #include +#include +#include #include #include -#include #include #include #include #include #include - +#include PANEL_SETUP_RULES::PANEL_SETUP_RULES( PAGED_DIALOG* aParent, PCB_EDIT_FRAME* aFrame ) : PANEL_SETUP_RULES_BASE( aParent->GetTreebook() ), @@ -372,9 +373,11 @@ bool PANEL_SETUP_RULES::TransferDataFromWindow() return false; } - if( m_textEditor->SaveFile( m_frame->Prj().AbsolutePath( "drc-rules" ) ) ) + wxString rulesFilepath = m_frame->Prj().AbsolutePath( "drc-rules" ); + + if( m_textEditor->SaveFile( rulesFilepath ) ) { - m_frame->GetToolManager()->GetTool()->LoadRules(); + m_frame->GetBoard()->GetDesignSettings().m_DRCEngine->LoadRules( rulesFilepath ); return true; } diff --git a/pcbnew/drc/drc.cpp b/pcbnew/drc/drc.cpp deleted file mode 100644 index 908b2284b4..0000000000 --- a/pcbnew/drc/drc.cpp +++ /dev/null @@ -1,101 +0,0 @@ -/* - * This program source code file is part of KiCad, a free EDA CAD application. - * - * Copyright (C) 2004-2019 Jean-Pierre Charras, jp.charras at wanadoo.fr - * Copyright (C) 2014 Dick Hollenbeck, dick@softplc.com - * Copyright (C) 2017-2020 KiCad Developers, see change_log.txt for contributors. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, you may find one here: - * http://www.gnu.org/licenses/old-licenses/gpl-2.0.html - * or you may search the http://www.gnu.org website for the version 2 license, - * or you may write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - - -DRC::DRC() : - PCB_TOOL_BASE( "pcbnew.legacyDRCTool" ), - m_editFrame( nullptr ) -{ -} - - -DRC::~DRC() -{ -} - - -void DRC::Reset( RESET_REASON aReason ) -{ - m_editFrame = getEditFrame(); -} - - -// JEY TODO: make DRC_TOOL's DRC_ENGINE be long-lived so it can be used for BOARD_CONNECTED_ITEM's -// GetClearance() and the retire this. - -bool DRC::LoadRules() -{ - wxString rulesFilepath = m_editFrame->Prj().AbsolutePath( "drc-rules" ); - wxFileName rulesFile( rulesFilepath ); - - if( rulesFile.FileExists() ) - { - m_rules.clear(); - - FILE* fp = wxFopen( rulesFilepath, wxT( "rt" ) ); - - if( fp ) - { - try - { - DRC_RULES_PARSER parser( m_editFrame->GetBoard(), fp, rulesFilepath ); - parser.Parse( m_rules, &NULL_REPORTER::GetInstance() ); - } - catch( PARSE_ERROR& pe ) - { - // Don't leave possibly malformed stuff around for us to trip over - m_rules.clear(); - - wxSafeYield( m_editFrame ); - m_editFrame->ShowBoardSetupDialog( _( "Rules" ), pe.What(), ID_RULES_EDITOR, - pe.lineNumber, pe.byteIndex ); - - return false; - } - } - } - - std::reverse( std::begin( m_rules ), std::end( m_rules ) ); - - BOARD_DESIGN_SETTINGS& bds = m_editFrame->GetBoard()->GetDesignSettings(); - bds.m_DRCRules = m_rules; - - return true; -} - - diff --git a/pcbnew/drc/drc.h b/pcbnew/drc/drc.h deleted file mode 100644 index 5651c707ce..0000000000 --- a/pcbnew/drc/drc.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * This program source code file is part of KiCad, a free EDA CAD application. - * - * Copyright (C) 2007-2016 Dick Hollenbeck, dick@softplc.com - * Copyright (C) 2017-2019 KiCad Developers, see change_log.txt for contributors. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, you may find one here: - * http://www.gnu.org/licenses/old-licenses/gpl-2.0.html - * or you may search the http://www.gnu.org website for the version 2 license, - * or you may write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA - */ - -#ifndef DRC_H -#define DRC_H - -#include -#include -#include -#include -#include -#include -#include -#include -#include - - -class PCB_EDIT_FRAME; - - -/** - * Design Rule Checker object that performs all the DRC tests. The output of - * the checking goes to the BOARD file in the form of two MARKER lists. Those - * two lists are displayable in the drc dialog box. And they can optionally - * be sent to a text file on disk. - * This class is given access to the windows and the BOARD - * that it needs via its constructor or public access functions. - */ -class DRC : public PCB_TOOL_BASE -{ -public: - DRC(); - ~DRC(); - - /// @copydoc TOOL_INTERACTIVE::Reset() - void Reset( RESET_REASON aReason ) override; - -private: - PCB_EDIT_FRAME* m_editFrame; // The pcb frame editor which owns the board - - std::vector m_rules; -public: - /** - * Load the DRC rules. Must be called after the netclasses have been read. - */ - bool LoadRules(); -}; - - -#endif // DRC_H diff --git a/pcbnew/drc/drc_engine.cpp b/pcbnew/drc/drc_engine.cpp index 38e336bdaf..f0ca91b7ab 100644 --- a/pcbnew/drc/drc_engine.cpp +++ b/pcbnew/drc/drc_engine.cpp @@ -31,7 +31,6 @@ #include #include #include -#include void drcPrintDebugMessage( int level, const wxString& msg, const char *function, int line ) { @@ -162,40 +161,47 @@ void DRC_ENGINE::loadImplicitRules() // 3) per-netclass rules - std::vector netclasses; + int ruleCount = 0; - m_board->SynchronizeNetsAndNetClasses(); - netclasses.push_back( bds.GetNetClasses().GetDefault() ); + auto makeNetclassRule = + [&]( const NETCLASSPTR& nc, bool isDefault ) + { + wxString className = nc->GetName(); + wxString expr; - for( const std::pair& netclass : bds.GetNetClasses() ) - netclasses.push_back( netclass.second ); + if( !isDefault ) + { + expr = wxString::Format( "A.NetClass == '%s' || B.NetClass == '%s'", + className, + className ); + } - ReportAux( wxString::Format( "Building %d implicit netclass rules", (int) netclasses.size() ) ); + DRC_RULE_CONDITION* inNetclassCondition = new DRC_RULE_CONDITION ( expr ); + DRC_RULE* rule = createImplicitRule( wxString::Format( _( "netclass '%s'" ), + className )); - for( const NETCLASSPTR& nc : netclasses ) - { - wxString className = nc->GetName(); - wxString expr = wxString::Format( "A.NetClass == '%s' || B.NetClass == '%s'", - className, - className ); + rule->m_Condition = inNetclassCondition; - DRC_RULE_CONDITION* inNetclassCondition = new DRC_RULE_CONDITION ( expr ); + // Only add netclass clearances if they're larger than board minimums. That way + // board minimums will still enforce a global minimum. - DRC_RULE* netclassRule = createImplicitRule( wxString::Format( _( "netclass '%s'" ), - className )); + if( nc->GetClearance() > bds.m_MinClearance ) + { + DRC_CONSTRAINT ncClearanceConstraint( DRC_CONSTRAINT_TYPE_CLEARANCE ); + ncClearanceConstraint.Value().SetMin( nc->GetClearance() ); + rule->AddConstraint( ncClearanceConstraint ); + } - netclassRule->m_Condition = inNetclassCondition; + ruleCount++; + }; - // Only add netclass clearances if they're larger than board minimums. That way - // board minimums will still enforce a global minimum. + m_board->SynchronizeNetsAndNetClasses(); + makeNetclassRule( bds.GetNetClasses().GetDefault(), true ); - if( nc->GetClearance() > bds.m_MinClearance ) - { - DRC_CONSTRAINT ncClearanceConstraint( DRC_CONSTRAINT_TYPE_CLEARANCE ); - ncClearanceConstraint.Value().SetMin( nc->GetClearance() ); - netclassRule->AddConstraint( ncClearanceConstraint ); - } - } + for( const std::pair& netclass : bds.GetNetClasses() ) + makeNetclassRule( netclass.second, false ); + + ReportAux( wxString::Format( "Building %d implicit netclass rules", ruleCount ) ); } static wxString formatConstraint( const DRC_CONSTRAINT& constraint ) @@ -425,14 +431,14 @@ void DRC_ENGINE::RunTests( EDA_UNITS aUnits, bool aTestTracksAgainstZones, DRC_CONSTRAINT DRC_ENGINE::EvalRulesForItems( DRC_CONSTRAINT_TYPE_T aConstraintId, - BOARD_ITEM* a, BOARD_ITEM* b, PCB_LAYER_ID aLayer, - REPORTER* aReporter ) + const BOARD_ITEM* a, const BOARD_ITEM* b, + PCB_LAYER_ID aLayer, REPORTER* aReporter ) { #define REPORT( s ) { if( aReporter ) { aReporter->Report( s ); } } #define UNITS aReporter ? aReporter->GetUnits() : EDA_UNITS::MILLIMETRES - auto* connectedA = a && a->IsConnected() ? static_cast( a ) : nullptr; - auto* connectedB = b && b->IsConnected() ? static_cast( b ) : nullptr; + const BOARD_CONNECTED_ITEM* connectedA = dynamic_cast( a ); + const BOARD_CONNECTED_ITEM* connectedB = dynamic_cast( b ); // Local overrides take precedence if( aConstraintId == DRC_CONSTRAINT_TYPE_CLEARANCE ) diff --git a/pcbnew/drc/drc_engine.h b/pcbnew/drc/drc_engine.h index da82e4dfb4..369accea06 100644 --- a/pcbnew/drc/drc_engine.h +++ b/pcbnew/drc/drc_engine.h @@ -97,6 +97,11 @@ public: m_violationHandler = std::move( aHandler ); } + void ClearViolationHandler() + { + m_violationHandler = DRC_VIOLATION_HANDLER(); + } + /* * Receives progress information to show the user. */ @@ -123,8 +128,8 @@ public: bool IsErrorLimitExceeded( int error_code ); - DRC_CONSTRAINT EvalRulesForItems( DRC_CONSTRAINT_TYPE_T ruleID, BOARD_ITEM* a, - BOARD_ITEM* b = nullptr, + DRC_CONSTRAINT EvalRulesForItems( DRC_CONSTRAINT_TYPE_T ruleID, const BOARD_ITEM* a, + const BOARD_ITEM* b = nullptr, PCB_LAYER_ID aLayer = UNDEFINED_LAYER, REPORTER* aReporter = nullptr ); diff --git a/pcbnew/drc/drc_item.cpp b/pcbnew/drc/drc_item.cpp index bd4fa0be9e..bde5744d30 100644 --- a/pcbnew/drc/drc_item.cpp +++ b/pcbnew/drc/drc_item.cpp @@ -27,7 +27,6 @@ #include #include "wx/html/m_templ.h" #include "wx/html/styleparams.h" -#include #include #include @@ -277,46 +276,3 @@ wxString escapeHtml( wxString aString ) } -wxString DRC_ITEM::ShowHtml( PCB_BASE_FRAME* aFrame ) const -{ - BOARD_ITEM* mainItem = nullptr; - BOARD_ITEM* auxItem = nullptr; - wxString msg = m_errorMessage.IsEmpty() ? GetErrorText() : m_errorMessage; - wxString mainText; - wxString auxText; - - if( m_mainItemUuid != niluuid ) - mainItem = aFrame->GetBoard()->GetItem( m_mainItemUuid ); - - if( m_auxItemUuid != niluuid ) - auxItem = aFrame->GetBoard()->GetItem( m_auxItemUuid ); - - if( mainItem ) - mainText = mainItem->GetSelectMenuText( aFrame->GetUserUnits() ); - - if( auxItem ) - auxText = auxItem->GetSelectMenuText( aFrame->GetUserUnits() ); - - if( mainItem && auxItem ) - { - // an html fragment for the entire message in the listbox. feel free - // to add color if you want: - return wxString::Format( wxT( "%s
   %s
   %s" ), - escapeHtml( msg ), - escapeHtml( mainText ), - escapeHtml( auxText ) ); - } - else if( mainItem ) - { - return wxString::Format( wxT( "%s
   %s" ), - escapeHtml( msg ), - escapeHtml( mainText ) ); - } - else - { - return wxString::Format( wxT( "%s" ), - escapeHtml( msg ) ); - } -} - - diff --git a/pcbnew/drc/drc_item.h b/pcbnew/drc/drc_item.h index 2c9adb9b8f..aa7f8c003a 100644 --- a/pcbnew/drc/drc_item.h +++ b/pcbnew/drc/drc_item.h @@ -97,13 +97,6 @@ public: return allItemTypes; } - /** - * Translates this object into a fragment of HTML suitable for the wxHtmlListBox class. - * @return wxString - the html text. - */ - wxString ShowHtml( PCB_BASE_FRAME* aFrame ) const; // JEY TODO - wxString FormatHtml( ) const { return ""; } // fixme - void SetViolatingRule ( DRC_RULE *aRule ) { m_violatingRule = aRule; } DRC_RULE* GetViolatingRule() const { return m_violatingRule; } diff --git a/pcbnew/drc/drc_rule.cpp b/pcbnew/drc/drc_rule.cpp index 107ba9993d..7daf8561eb 100644 --- a/pcbnew/drc/drc_rule.cpp +++ b/pcbnew/drc/drc_rule.cpp @@ -29,54 +29,6 @@ #include -const DRC_CONSTRAINT* GetConstraint( const BOARD_ITEM* aItem, const BOARD_ITEM* bItem, - int aConstraint, PCB_LAYER_ID aLayer, wxString* aRuleName ) -{ - BOARD* board = aItem->GetBoard(); - - if( !board ) - return nullptr; - - for( DRC_RULE* rule : board->GetDesignSettings().m_DRCRules ) - { - if( !rule->m_LayerCondition.test( aLayer ) ) - continue; - - const DRC_CONSTRAINT* constraint = nullptr; - - for( const DRC_CONSTRAINT& candidate : rule->m_Constraints ) - { - if( candidate.m_Type == aConstraint ) - { - constraint = &candidate; - break; - } - } - - if( constraint ) - { - if( rule->m_Condition->EvaluateFor( aItem, bItem, aLayer ) ) - { - if( aRuleName ) - *aRuleName = rule->m_Name; - - return constraint; - } - - if( bItem && rule->m_Condition->EvaluateFor( bItem, aItem, aLayer ) ) - { - if( aRuleName ) - *aRuleName = rule->m_Name; - - return constraint; - } - } - } - - return nullptr; -} - - DRC_RULE::DRC_RULE() : m_Unary( false ), m_Implicit( false ), diff --git a/pcbnew/drc/drc_test_provider_annulus.cpp b/pcbnew/drc/drc_test_provider_annulus.cpp index b2716c37c8..aaadb4b469 100644 --- a/pcbnew/drc/drc_test_provider_annulus.cpp +++ b/pcbnew/drc/drc_test_provider_annulus.cpp @@ -24,7 +24,6 @@ #include #include #include -#include #include #include #include diff --git a/pcbnew/drc/drc_test_provider_connectivity.cpp b/pcbnew/drc/drc_test_provider_connectivity.cpp index d22fdae79b..9db9d79ce1 100644 --- a/pcbnew/drc/drc_test_provider_connectivity.cpp +++ b/pcbnew/drc/drc_test_provider_connectivity.cpp @@ -28,7 +28,6 @@ #include #include -#include #include #include #include diff --git a/pcbnew/drc/drc_test_provider_copper_clearance.cpp b/pcbnew/drc/drc_test_provider_copper_clearance.cpp index 394c8d6176..1877f51802 100644 --- a/pcbnew/drc/drc_test_provider_copper_clearance.cpp +++ b/pcbnew/drc/drc_test_provider_copper_clearance.cpp @@ -25,15 +25,15 @@ #include #include #include +#include -#include +//#include #include #include #include #include #include -#include #include #include #include diff --git a/pcbnew/drc/drc_test_provider_courtyard_clearance.cpp b/pcbnew/drc/drc_test_provider_courtyard_clearance.cpp index 6d9263ca1b..f4d3154f57 100644 --- a/pcbnew/drc/drc_test_provider_courtyard_clearance.cpp +++ b/pcbnew/drc/drc_test_provider_courtyard_clearance.cpp @@ -23,7 +23,6 @@ #include #include -#include #include #include #include diff --git a/pcbnew/drc/drc_test_provider_disallow.cpp b/pcbnew/drc/drc_test_provider_disallow.cpp index 377a39861f..e6481983cc 100644 --- a/pcbnew/drc/drc_test_provider_disallow.cpp +++ b/pcbnew/drc/drc_test_provider_disallow.cpp @@ -23,7 +23,6 @@ #include #include -#include #include #include #include diff --git a/pcbnew/drc/drc_test_provider_edge_clearance.cpp b/pcbnew/drc/drc_test_provider_edge_clearance.cpp index afffd85d1c..dee28089d6 100644 --- a/pcbnew/drc/drc_test_provider_edge_clearance.cpp +++ b/pcbnew/drc/drc_test_provider_edge_clearance.cpp @@ -28,7 +28,6 @@ #include #include #include -#include #include /* diff --git a/pcbnew/drc/drc_test_provider_hole_clearance.cpp b/pcbnew/drc/drc_test_provider_hole_clearance.cpp index d9d11e27be..698a230daf 100644 --- a/pcbnew/drc/drc_test_provider_hole_clearance.cpp +++ b/pcbnew/drc/drc_test_provider_hole_clearance.cpp @@ -24,11 +24,11 @@ #include #include #include +#include #include #include #include #include -#include #include /* diff --git a/pcbnew/drc/drc_test_provider_hole_size.cpp b/pcbnew/drc/drc_test_provider_hole_size.cpp index 1a091ef8ee..f8c42ed1f0 100644 --- a/pcbnew/drc/drc_test_provider_hole_size.cpp +++ b/pcbnew/drc/drc_test_provider_hole_size.cpp @@ -22,10 +22,10 @@ */ #include +#include #include #include #include -#include #include diff --git a/pcbnew/drc/drc_test_provider_lvs.cpp b/pcbnew/drc/drc_test_provider_lvs.cpp index 2c0d459e04..e6aba21ff1 100644 --- a/pcbnew/drc/drc_test_provider_lvs.cpp +++ b/pcbnew/drc/drc_test_provider_lvs.cpp @@ -23,7 +23,6 @@ #include #include -#include #include #include #include diff --git a/pcbnew/drc/drc_test_provider_misc.cpp b/pcbnew/drc/drc_test_provider_misc.cpp index 69f5d4db55..c300ef6e6b 100644 --- a/pcbnew/drc/drc_test_provider_misc.cpp +++ b/pcbnew/drc/drc_test_provider_misc.cpp @@ -23,7 +23,6 @@ #include #include -#include #include #include #include diff --git a/pcbnew/drc/drc_test_provider_track_width.cpp b/pcbnew/drc/drc_test_provider_track_width.cpp index 674f80023f..fb2cab3e52 100644 --- a/pcbnew/drc/drc_test_provider_track_width.cpp +++ b/pcbnew/drc/drc_test_provider_track_width.cpp @@ -24,7 +24,6 @@ //#include #include #include -#include #include #include #include diff --git a/pcbnew/drc/drc_test_provider_via_diameter.cpp b/pcbnew/drc/drc_test_provider_via_diameter.cpp index e92637a23b..9ae8552246 100644 --- a/pcbnew/drc/drc_test_provider_via_diameter.cpp +++ b/pcbnew/drc/drc_test_provider_via_diameter.cpp @@ -23,7 +23,6 @@ #include #include -#include #include #include #include diff --git a/pcbnew/footprint_editor_settings.cpp b/pcbnew/footprint_editor_settings.cpp index 8746e4028f..f7a3a2ac6f 100644 --- a/pcbnew/footprint_editor_settings.cpp +++ b/pcbnew/footprint_editor_settings.cpp @@ -27,7 +27,6 @@ #include #include #include -#include #include extern const char* traceSettings; diff --git a/pcbnew/menubar_pcb_editor.cpp b/pcbnew/menubar_pcb_editor.cpp index 1438bc8062..3ccdd2fa17 100644 --- a/pcbnew/menubar_pcb_editor.cpp +++ b/pcbnew/menubar_pcb_editor.cpp @@ -26,7 +26,6 @@ #include -#include #include #include #include diff --git a/pcbnew/pcb_base_edit_frame.cpp b/pcbnew/pcb_base_edit_frame.cpp index 9d05627d14..372e311be8 100644 --- a/pcbnew/pcb_base_edit_frame.cpp +++ b/pcbnew/pcb_base_edit_frame.cpp @@ -131,6 +131,10 @@ void PCB_BASE_EDIT_FRAME::SetBoard( BOARD* aBoard ) if( new_board ) { + BOARD_DESIGN_SETTINGS& bds = aBoard->GetDesignSettings(); + bds.m_DRCEngine = std::make_shared( aBoard, &bds ); + bds.m_DRCEngine->InitEngine( Prj().AbsolutePath( "drc-rules" ) ); + if( m_toolManager ) m_toolManager->ResetTools( TOOL_BASE::MODEL_RELOAD ); diff --git a/pcbnew/pcb_edit_frame.cpp b/pcbnew/pcb_edit_frame.cpp index e2b9519592..d97d3ab77f 100644 --- a/pcbnew/pcb_edit_frame.cpp +++ b/pcbnew/pcb_edit_frame.cpp @@ -30,7 +30,6 @@ #include #include #include -#include #include #include #include @@ -504,7 +503,6 @@ void PCB_EDIT_FRAME::setupTools() m_toolManager->RegisterTool( new POSITION_RELATIVE_TOOL ); m_toolManager->RegisterTool( new ZONE_FILLER_TOOL ); m_toolManager->RegisterTool( new AUTOPLACE_TOOL ); - m_toolManager->RegisterTool( new DRC ); m_toolManager->RegisterTool( new DRC_TOOL ); m_toolManager->RegisterTool( new PCB_VIEWER_TOOLS ); m_toolManager->RegisterTool( new CONVERT_TOOL ); @@ -1046,8 +1044,6 @@ void PCB_EDIT_FRAME::onBoardLoaded() SetMsgPanel( GetBoard() ); SetStatusText( wxEmptyString ); - m_toolManager->GetTool()->LoadRules(); - KIPLATFORM::APP::SetShutdownBlockReason( this, _( "PCB file changes are unsaved" ) ); } diff --git a/pcbnew/tools/drc_tool.cpp b/pcbnew/tools/drc_tool.cpp index 0d073d68b8..bdb6931a56 100644 --- a/pcbnew/tools/drc_tool.cpp +++ b/pcbnew/tools/drc_tool.cpp @@ -62,6 +62,7 @@ void DRC_TOOL::Reset( RESET_REASON aReason ) DestroyDRCDialog( wxID_OK ); m_pcb = m_editFrame->GetBoard(); + m_drcEngine = m_pcb->GetDesignSettings().m_DRCEngine; } } @@ -131,10 +132,8 @@ void DRC_TOOL::RunTests( WX_PROGRESS_REPORTER* aProgressReporter, bool aTestTrac bool aRefillZones, bool aReportAllTrackErrors, bool aTestFootprints ) { ZONE_FILLER_TOOL* zoneFiller = m_toolMgr->GetTool(); - - BOARD_COMMIT commit( m_editFrame ); - DRC_ENGINE drcEngine( m_pcb, &m_pcb->GetDesignSettings() ); - NETLIST netlist; + BOARD_COMMIT commit( m_editFrame ); + NETLIST netlist; if( aRefillZones ) { @@ -149,9 +148,10 @@ void DRC_TOOL::RunTests( WX_PROGRESS_REPORTER* aProgressReporter, bool aTestTrac zoneFiller->CheckAllZones( aProgressReporter->GetParent(), aProgressReporter ); } - drcEngine.InitEngine( m_editFrame->Prj().AbsolutePath( "drc-rules" ) ); - - drcEngine.SetWorksheet( m_editFrame->GetCanvas()->GetWorksheet() ); + // Re-initialize the DRC_ENGINE to make doubly sure everything is up-to-date + // + m_drcEngine->InitEngine( m_editFrame->Prj().AbsolutePath( "drc-rules" ) ); + m_drcEngine->SetWorksheet( m_editFrame->GetCanvas()->GetWorksheet() ); if( aTestFootprints && !Kiface().IsSingle() ) { @@ -160,12 +160,12 @@ void DRC_TOOL::RunTests( WX_PROGRESS_REPORTER* aProgressReporter, bool aTestTrac if( m_drcDialog ) m_drcDialog->Raise(); - drcEngine.SetSchematicNetlist( &netlist ); + m_drcEngine->SetSchematicNetlist( &netlist ); } - drcEngine.SetProgressReporter( aProgressReporter ); + m_drcEngine->SetProgressReporter( aProgressReporter ); - drcEngine.SetViolationHandler( + m_drcEngine->SetViolationHandler( [&]( const std::shared_ptr& aItem, wxPoint aPos ) { if( aItem->GetErrorCode() == DRCE_MISSING_FOOTPRINT @@ -186,8 +186,11 @@ void DRC_TOOL::RunTests( WX_PROGRESS_REPORTER* aProgressReporter, bool aTestTrac } } ); - drcEngine.RunTests( m_editFrame->GetUserUnits(), aTestTracksAgainstZones, - aReportAllTrackErrors, aTestFootprints ); + m_drcEngine->RunTests( m_editFrame->GetUserUnits(), aTestTracksAgainstZones, + aReportAllTrackErrors, aTestFootprints ); + + m_drcEngine->SetProgressReporter( nullptr ); + m_drcEngine->ClearViolationHandler(); commit.Push( _( "DRC" ), false ); diff --git a/pcbnew/tools/drc_tool.h b/pcbnew/tools/drc_tool.h index a8b61204fa..80083f8956 100644 --- a/pcbnew/tools/drc_tool.h +++ b/pcbnew/tools/drc_tool.h @@ -39,12 +39,11 @@ class PCB_EDIT_FRAME; class DIALOG_DRC; class DRC_ITEM; class WX_PROGRESS_REPORTER; +class DRC_ENGINE; class DRC_TOOL : public PCB_TOOL_BASE { - friend class DIALOG_DRC; - public: DRC_TOOL(); ~DRC_TOOL(); @@ -57,6 +56,8 @@ private: BOARD* m_pcb; DIALOG_DRC* m_drcDialog; + std::shared_ptr m_drcEngine; + std::vector> m_unconnected; // list of unconnected pads std::vector> m_footprints; // list of footprint warnings diff --git a/pcbnew/tools/pcb_inspection_tool.cpp b/pcbnew/tools/pcb_inspection_tool.cpp index d5bb692bcf..4099da0d2e 100644 --- a/pcbnew/tools/pcb_inspection_tool.cpp +++ b/pcbnew/tools/pcb_inspection_tool.cpp @@ -198,11 +198,6 @@ void PCB_INSPECTION_TOOL::reportCopperClearance( PCB_LAYER_ID aLayer, BOARD_CONN r->Report( "" ); r->Report( wxString::Format( _( "Clearance: %s." ), clearance ) ); } - - // JEY TODO: hook this up to new DRC engine to get "classic" sources as well; right now - // we're just reporting on rules.... - // JEY TODO: retire this version - // aA->GetClearance( aLayer, aB, &source, r ); } diff --git a/pcbnew/zones_by_polygon.cpp b/pcbnew/zones_by_polygon.cpp index cf97b62856..1edf3dbce0 100644 --- a/pcbnew/zones_by_polygon.cpp +++ b/pcbnew/zones_by_polygon.cpp @@ -35,7 +35,6 @@ #include #include #include -#include #include #include #include diff --git a/qa/drc_proto/drc_test_provider_silk_to_pad.cpp b/qa/drc_proto/drc_test_provider_silk_to_pad.cpp index e7ee20475e..39cbd9c8ff 100644 --- a/qa/drc_proto/drc_test_provider_silk_to_pad.cpp +++ b/qa/drc_proto/drc_test_provider_silk_to_pad.cpp @@ -33,11 +33,10 @@ #include #include -#include -#include +#include #include #include -#include +#include /* Silk to pads clearance test. Check all pads against silkscreen (mask opening in the pad vs silkscreen) diff --git a/qa/pcbnew_utils/board_construction_utils.cpp b/qa/pcbnew_utils/board_construction_utils.cpp index 30d6b206ad..1f89df3772 100644 --- a/qa/pcbnew_utils/board_construction_utils.cpp +++ b/qa/pcbnew_utils/board_construction_utils.cpp @@ -25,8 +25,6 @@ #include #include -#include - #include #include