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Re-enable tests for zones 

Avoid invalid substantial checks triggered by signed floating point
zeros.  Adds a QA check to ensure zone-self checks are maintained
7.0
Seth Hillbrand 3 years ago
parent
5ed7e28252
commit
b9461f2ba7
4 changed files with 201 additions and 20 deletions
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  1. 61
      pcbnew/drc/drc_test_provider_connection_width.cpp
  2. 150
      qa/data/pcbnew/issue9870.kicad_pcb
  3. 8
      qa/data/pcbnew/issue9870.kicad_pro
  4. 2
      qa/unittests/pcbnew/drc/test_drc_copper_conn.cpp

61
pcbnew/drc/drc_test_provider_connection_width.cpp
View File

@ -88,8 +88,8 @@ private:
class POLYGON_TEST
{
public:
POLYGON_TEST( int aLimit ) :
m_limit( aLimit )
POLYGON_TEST( int aLimit, int aErrorLimit ) :
m_limit( aLimit ), m_max_error( aErrorLimit )
{
};
@ -339,16 +339,28 @@ private:
p = p0->next;
}
while( p0 != aB && checked < total_pts && directions != 15 )
while( p0 != aB && checked < total_pts && directions != 0b1111 )
{
int bit2x = std::signbit( p->x - p0->x );
int bit2y = std::signbit( p->y - p0->y );
directions |= ( 1 << ( 2 + bit2x ) ) + ( 1 << bit2y );
double diff_x = std::abs( p->x - p0->x );
double diff_y = std::abs( p->y - p0->y );
p0 = p;
if( same_point( p0, p0->nextZ ) )
// Floating point zeros can have a negative sign, so we need to
// ensure that only substantive diversions count for a direction
// change
if( diff_x > m_max_error )
directions |= ( 1 << ( 2 + std::signbit( p->x - p0->x ) ) );
if( diff_y > m_max_error )
directions |= ( 1 << std::signbit( p->y - p0->y ) );
// In the case of a circle, we need to eventually get the direction
// so keep the p0 at the same point
if( diff_x > m_max_error || diff_y > m_max_error || p == aB )
p0 = p;
if( same_point( p, p->nextZ ) )
p = p->nextZ->next;
else if( same_point( p0, p0->prevZ ) )
else if( same_point( p, p->prevZ ) )
p = p->prevZ->next;
else
p = p->next;
@ -383,13 +395,24 @@ private:
directions = 0;
checked = 0;
while( p0 != aB && checked < total_pts && directions != 15 )
while( p0 != aB && checked < total_pts && directions != 0b1111 )
{
int bit2x = std::signbit( p->x - p0->x );
int bit2y = std::signbit( p->y - p0->y );
directions |= ( 1 << ( 2 + bit2x ) ) + ( 1 << bit2y );
double diff_x = std::abs( p->x - p0->x );
double diff_y = std::abs( p->y - p0->y );
p0 = p;
// Floating point zeros can have a negative sign, so we need to
// ensure that only substantive diversions count for a direction
// change
if( diff_x > m_max_error )
directions |= ( 1 << ( 2 + std::signbit( p->x - p0->x ) ) );
if( diff_y > m_max_error )
directions |= ( 1 << std::signbit( p->y - p0->y ) );
// In the case of a circle, we need to eventually get the direction
// so keep the p0 at the same point
if( diff_x > m_max_error || diff_y > m_max_error || p == aB )
p0 = p;
if( same_point( p, p->nextZ ) )
p = p->nextZ->prev;
@ -550,6 +573,7 @@ private:
private:
int m_limit;
double m_max_error;
BOX2I m_bbox;
std::deque<Vertex> m_vertices;
std::set<std::pair<int, int>> m_hits;
@ -637,7 +661,7 @@ bool DRC_TEST_PROVIDER_CONNECTION_WIDTH::Run()
if( m_drcEngine->IsCancelled() )
return 0;
POLYGON_TEST test( aMinWidth );
POLYGON_TEST test( aMinWidth, m_drcEngine->GetDesignSettings()->m_MaxError );
for( int ii = 0; ii < aDataset.poly.OutlineCount(); ++ii )
{
@ -662,6 +686,13 @@ bool DRC_TEST_PROVIDER_CONNECTION_WIDTH::Run()
items.push_back( item );
}
for( auto& [ zone, rtree ] : board->m_CopperZoneRTreeCache )
{
if( !rtree->GetObjectsAt( location, aLayer, aMinWidth ).empty() &&
zone->HitTestFilledArea( aLayer, location, aMinWidth ) )
items.push_back( zone );
}
if( !items.empty() )
{
DRC_CONSTRAINT c = m_drcEngine->EvalRules( CONNECTION_WIDTH_CONSTRAINT,

150
qa/data/pcbnew/issue9870.kicad_pcb
View File

@ -1,4 +1,4 @@
(kicad_pcb (version 20220609) (generator pcbnew)
(kicad_pcb (version 20220815) (generator pcbnew)
(general
(thickness 0)
@ -111,6 +111,8 @@
(gr_rect (start 119.5 69.1) (end 137.3 80.8)
(stroke (width 0.1) (type default)) (fill none) (layer "Edge.Cuts") (tstamp 8900a23a-a318-4bb8-8db1-6b52ef189e07))
(via (at 135.549127 77.119098) (size 1.651) (drill 0.635) (layers "F.Cu" "B.Cu") (free) (net 0) (tstamp 1465286a-4c08-44cc-866f-3e1182e75cf4))
(via (at 135.509077 74.208158) (size 1.651) (drill 0.635) (layers "F.Cu" "B.Cu") (free) (net 0) (tstamp 5275fdcc-80b0-4f9c-9611-4b1fafb55cf9))
(via (at 126.4 78.5) (size 1.651) (drill 0.635) (layers "F.Cu" "B.Cu") (net 1) (tstamp 84387f2a-9959-4d79-a875-53244f1f4e68))
(via (at 128.753787 79.665232) (size 0.5) (drill 0.2) (layers "F.Cu" "B.Cu") (net 1) (tstamp b06ca4b8-22df-4ec6-bf66-cf080ffc53d7))
(segment (start 121.060406 75.523254) (end 120.717987 74.4931) (width 0.635) (layer "B.Cu") (net 1) (tstamp 0d2541aa-78dc-4d71-8d09-70964c8b4654))
@ -189,4 +191,150 @@
)
)
)
(zone (net 1) (net_name "Net-(D1-Pad2)") (layer "B.Cu") (tstamp 3378247d-c173-4772-893a-c2e81018cea2) (hatch edge 0.508)
(connect_pads (clearance 0.508))
(min_thickness 0.254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.508) (thermal_bridge_width 0.508) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 137.09101 76.812004)
(xy 133.962002 76.812004)
(xy 133.962002 74.636898)
(xy 137.09101 74.636898)
)
)
(filled_polygon
(layer "B.Cu")
(island)
(pts
(xy 134.224945 74.6569)
(xy 134.271019 74.709648)
(xy 134.34706 74.872719)
(xy 134.347063 74.872724)
(xy 134.349386 74.877706)
(xy 134.48327 75.068912)
(xy 134.648323 75.233965)
(xy 134.652831 75.237122)
(xy 134.652834 75.237124)
(xy 134.83502 75.364692)
(xy 134.839529 75.367849)
(xy 134.844511 75.370172)
(xy 134.844516 75.370175)
(xy 135.046097 75.464174)
(xy 135.051079 75.466497)
(xy 135.056387 75.467919)
(xy 135.056389 75.46792)
(xy 135.27123 75.525486)
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(xy 135.276545 75.52691)
(xy 135.407259 75.538346)
(xy 135.424552 75.539859)
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(xy 135.529654 75.619559)
(xy 135.556963 75.571378)
(xy 135.619808 75.538346)
(xy 135.633651 75.536355)
(xy 135.741609 75.52691)
(xy 135.746922 75.525486)
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(xy 135.961765 75.46792)
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(xy 136.001815 75.859336)
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(xy 135.786972 75.80177)
(xy 135.781659 75.800346)
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)
)
)
)

8
qa/data/pcbnew/issue9870.kicad_pro
View File

@ -404,7 +404,7 @@
"pinned_symbol_libs": []
},
"meta": {
"filename": "small_conn.kicad_pro",
"filename": "issue9870.kicad_pro",
"version": 1
},
"net_settings": {
@ -428,9 +428,11 @@
}
],
"meta": {
"version": 2
"version": 3
},
"net_colors": null
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
},
"pcbnew": {
"last_paths": {

2
qa/unittests/pcbnew/drc/test_drc_copper_conn.cpp
View File

@ -50,7 +50,7 @@ BOOST_FIXTURE_TEST_CASE( DRCCopperConn, DRC_REGRESSION_TEST_FIXTURE )
std::vector<std::pair<wxString, int>> tests =
{
{ "issue9870", 12 },
{ "issue9870", 13 },
{ "connection_width_rules", 3 }
};

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