Re-resolve netclasses after assigning netclass to pattern.

Fixes https://gitlab.com/kicad/code/kicad/issues/12965

pcbnew/board.cpp

@@ -1467,7 +1467,7 @@ void BOARD::SynchronizeProperties()
 }
 
 
-void BOARD::SynchronizeNetsAndNetClasses()
+void BOARD::SynchronizeNetsAndNetClasses( bool aResetTrackAndViaSizes )
 {
     if( !m_project )
         return;
@@ -1478,15 +1478,18 @@ void BOARD::SynchronizeNetsAndNetClasses()
     for( NETINFO_ITEM* net : m_NetInfo )
         net->SetNetClass( bds.m_NetSettings->GetEffectiveNetClass( net->GetNetname() ) );
 
-    // Set initial values for custom track width & via size to match the default
-    // netclass settings
-    bds.UseCustomTrackViaSize( false );
-    bds.SetCustomTrackWidth( defaultNetClass->GetTrackWidth() );
-    bds.SetCustomViaSize( defaultNetClass->GetViaDiameter() );
-    bds.SetCustomViaDrill( defaultNetClass->GetViaDrill() );
-    bds.SetCustomDiffPairWidth( defaultNetClass->GetDiffPairWidth() );
-    bds.SetCustomDiffPairGap( defaultNetClass->GetDiffPairGap() );
-    bds.SetCustomDiffPairViaGap( defaultNetClass->GetDiffPairViaGap() );
+    if( aResetTrackAndViaSizes )
+    {
+        // Set initial values for custom track width & via size to match the default
+        // netclass settings
+        bds.UseCustomTrackViaSize( false );
+        bds.SetCustomTrackWidth( defaultNetClass->GetTrackWidth() );
+        bds.SetCustomViaSize( defaultNetClass->GetViaDiameter() );
+        bds.SetCustomViaDrill( defaultNetClass->GetViaDrill() );
+        bds.SetCustomDiffPairWidth( defaultNetClass->GetDiffPairWidth() );
+        bds.SetCustomDiffPairGap( defaultNetClass->GetDiffPairGap() );
+        bds.SetCustomDiffPairViaGap( defaultNetClass->GetDiffPairViaGap() );
+    }
 
     InvokeListeners( &BOARD_LISTENER::OnBoardNetSettingsChanged, *this );
 }

pcbnew/board.h

@@ -869,7 +869,7 @@ public:
      * the list of nets)  Also this function removes the non existing nets in netclasses
      * and add net nets in default netclass (this happens after reading a netlist)
      */
-    void SynchronizeNetsAndNetClasses();
+    void SynchronizeNetsAndNetClasses( bool aResetTrackAndViaSizes );
 
     /**
      * Copy the current project's text variables into the boards property cache.

pcbnew/drc/drc_engine.cpp

@@ -371,7 +371,7 @@ void DRC_ENGINE::loadImplicitRules()
                 }
             };
 
-    m_board->SynchronizeNetsAndNetClasses();
+    m_board->SynchronizeNetsAndNetClasses( false );
     makeNetclassRules( bds.m_NetSettings->m_DefaultNetClass, true );
 
     for( const auto& [ name, netclass ] : bds.m_NetSettings->m_NetClasses )

pcbnew/files.cpp

@@ -1062,7 +1062,7 @@ bool PCB_EDIT_FRAME::SavePcbFile( const wxString& aFileName, bool addToHistory,
         SaveProjectSettings();
 
         GetBoard()->SynchronizeProperties();
-        GetBoard()->SynchronizeNetsAndNetClasses();
+        GetBoard()->SynchronizeNetsAndNetClasses( false );
     }
 
     wxString   tempFile = wxFileName::CreateTempFileName( "pcbnew" );
@@ -1167,7 +1167,7 @@ bool PCB_EDIT_FRAME::SavePcbCopy( const wxString& aFileName, bool aCreateProject
     // edited via the DRC dialog as well as the Board Setup dialog), DRC exclusions, etc.
     SaveProjectSettings();
 
-    GetBoard()->SynchronizeNetsAndNetClasses();
+    GetBoard()->SynchronizeNetsAndNetClasses( false );
 
     try
     {

pcbnew/initpcb.cpp

@@ -126,7 +126,7 @@ bool FOOTPRINT_EDIT_FRAME::Clear_Pcb( bool aQuery )
     BOARD* board = new BOARD;
 
     board->GetDesignSettings() = GetDesignSettings();
-    board->SynchronizeNetsAndNetClasses();
+    board->SynchronizeNetsAndNetClasses( true );
     SetBoard( board );
 
     // This board will only be used to hold a footprint for editing

pcbnew/netinfo_list.cpp

@@ -164,7 +164,7 @@ void NETINFO_LIST::buildListOfNets()
     for( NETINFO_ITEM* net : *this )
         net->Clear();
 
-    m_parent->SynchronizeNetsAndNetClasses( );
+    m_parent->SynchronizeNetsAndNetClasses( false );
     m_parent->SetAreasNetCodesFromNetNames();
 }
 

pcbnew/netlist_reader/board_netlist_updater.cpp

@@ -1085,7 +1085,7 @@ bool BOARD_NETLIST_UPDATER::UpdateNetlist( NETLIST& aNetlist )
         // * it is useless because zones will be refilled after placing new footprints
         m_commit.Push( _( "Update netlist" ), m_newFootprintsCount ? ZONE_FILL_OP  : 0 );
 
-        m_board->SynchronizeNetsAndNetClasses();
+        m_board->SynchronizeNetsAndNetClasses( true );
         m_frame->SaveProjectSettings();
     }
 

pcbnew/pcb_edit_frame.cpp

@@ -1123,7 +1123,7 @@ void PCB_EDIT_FRAME::ShowBoardSetupDialog( const wxString& aInitialPage )
 
     if( dlg.ShowQuasiModal() == wxID_OK )
     {
-        GetBoard()->SynchronizeNetsAndNetClasses();
+        GetBoard()->SynchronizeNetsAndNetClasses( true );
         SaveProjectSettings();
 
         Kiway().CommonSettingsChanged( false, true );

pcbnew/python/scripting/pcbnew_scripting_helpers.cpp

@@ -189,7 +189,7 @@ BOARD* LoadBoard( wxString& aFileName, IO_MGR::PCB_FILE_T aFormat )
 
         brd->BuildConnectivity();
         brd->BuildListOfNets();
-        brd->SynchronizeNetsAndNetClasses();
+        brd->SynchronizeNetsAndNetClasses( false );
     }
 
     return brd;
@@ -241,7 +241,7 @@ BOARD* CreateEmptyBoard()
 bool SaveBoard( wxString& aFileName, BOARD* aBoard, IO_MGR::PCB_FILE_T aFormat, bool aSkipSettings )
 {
     aBoard->BuildConnectivity();
-    aBoard->SynchronizeNetsAndNetClasses();
+    aBoard->SynchronizeNetsAndNetClasses( false );
 
     // Ensure the "C" locale is temporary set, before saving any file
     // It also avoid wxWidget alerts about locale issues, later, when using Python 3

pcbnew/specctra_import_export/specctra_export.cpp

@@ -130,7 +130,7 @@ void ExportBoardToSpecctraFile( BOARD* aBoard, const wxString& aFullFilename )
 
     try
     {
-        aBoard->SynchronizeNetsAndNetClasses();
+        aBoard->SynchronizeNetsAndNetClasses( false );
         db.FromBOARD( aBoard );
         db.ExportPCB( aFullFilename, true );
         db.RevertFOOTPRINTs( aBoard );

pcbnew/tools/board_editor_control.cpp

@@ -1522,7 +1522,8 @@ int BOARD_EDITOR_CONTROL::AssignNetclass( const TOOL_EVENT& aEvent )
                 canvas()->ForceRefresh();
             } );
 
-    dlg.ShowModal();
+    if( dlg.ShowModal() == wxID_OK )
+        board()->SynchronizeNetsAndNetClasses( false );
 
     return 0;
 }

pcbnew/tools/pcb_control.cpp

@@ -1279,7 +1279,7 @@ int PCB_CONTROL::AppendBoard( PLUGIN& pi, wxString& fileName )
 
     // rebuild nets and ratsnest before any use of nets
     brd->BuildListOfNets();
-    brd->SynchronizeNetsAndNetClasses();
+    brd->SynchronizeNetsAndNetClasses( true );
     brd->BuildConnectivity();
 
     // Synchronize layers