Add basic netlist QA test

6 years ago · 7df3df3381
31 changed files with 24107 additions and 36 deletions
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@ -129,6 +129,10 @@ option( KICAD_USE_VALGRIND
    "Build KiCad with valgrind stack tracking enabled."
    OFF )

+option( KICAD_NETLIST_QA
+    "Run eeschema netlist QA tests (requires Python 3)"
+    OFF )
+
 # when option KICAD_SCRIPTING OR KICAD_SCRIPTING_MODULES is enabled:
 # PYTHON_EXECUTABLE can be defined when invoking cmake
 # ( use -DPYTHON_EXECUTABLE=<python path>/python.exe or python2 )
--- a/qa/eeschema/CMakeLists.txt
+++ b/qa/eeschema/CMakeLists.txt
@ -100,3 +100,14 @@ set_source_files_properties( eeschema_test_utils.cpp PROPERTIES
 )

 kicad_add_boost_test( qa_eeschema eeschema )
+
+# eeschema netlist tests
+# technically this doesn't depend on KICAD_SCRIPTING but if we have that, we know we have Python.
+if( KICAD_SCRIPTING_MODULES AND KICAD_NETLIST_QA )
+
+    add_test( NAME qa_netlist
+        COMMAND ${PYTHON_EXECUTABLE} test_netlists.py ${CMAKE_BINARY_DIR}
+        WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
+    )
+
+endif()
--- a/qa/eeschema/data/netlists/complex_hierarchy/ampli_ht.sch
+++ b/qa/eeschema/data/netlists/complex_hierarchy/ampli_ht.sch
@ -0,0 +1,804 @@
+EESchema Schematic File Version 5
+EELAYER 30 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 2 3
+Title "Complex hierarchy: demo"
+Date "2017-01-15"
+Rev "1"
+Comp ""
+Comment1 ""
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+F 1 "LM358N" H 6550 5200 50  0000 C CNN
+F 2 "Package_DIP:DIP-8_W7.62mm_LongPads" H 6650 5150 10  0000 C CNN
+F 3 "" H 6400 5400 60  0001 C CNN
+	1    6400 5400
+	1    0    0    -1  
+$EndComp
+$Comp
+L complex_hierarchy_schlib:CONN_2 P6
+U 1 1 4B3A1367
+P 1350 2100
+AR Path="/4B3A13A4/4B3A1367" Ref="P6"  Part="1" 
+AR Path="/4B3A1333/4B3A1367" Ref="P4"  Part="1" 
+F 0 "P6" V 1300 2100 40  0000 C CNN
+F 1 "CONN_2" V 1400 2100 40  0000 C CNN
+F 2 "TerminalBlock_Altech:Altech_AK300_1x02_P5.00mm_45-Degree" H 1300 1900 10  0000 C CNN
+F 3 "" H 1350 2100 60  0001 C CNN
+	1    1350 2100
+	-1   0    0    -1  
+$EndComp
+$Comp
+L complex_hierarchy_schlib:C C7
+U 1 1 4B3A1366
+P 4000 2550
+AR Path="/4B3A13A4/4B3A1366" Ref="C7"  Part="1" 
+AR Path="/4B3A1333/4B3A1366" Ref="C4"  Part="1" 
+F 0 "C7" H 4100 2650 50  0000 L CNN
+F 1 "4.7nF" H 4100 2450 50  0000 L CNN
+F 2 "Capacitor_THT:C_Disc_D5.0mm_W2.5mm_P5.00mm" H 4150 2400 10  0000 C CNN
+F 3 "" H 4000 2550 60  0001 C CNN
+	1    4000 2550
+	1    0    0    -1  
+$EndComp
+$Comp
+L complex_hierarchy_schlib:C C8
+U 1 1 4B3A1365
+P 8100 5750
+AR Path="/4B3A13A4/4B3A1365" Ref="C8"  Part="1" 
+AR Path="/4B3A1333/4B3A1365" Ref="C5"  Part="1" 
+F 0 "C8" H 8150 5850 50  0000 L CNN
+F 1 "820pF" H 8150 5650 50  0000 L CNN
+F 2 "Capacitor_THT:C_Disc_D5.0mm_W2.5mm_P5.00mm" H 8300 5600 10  0000 C CNN
+F 3 "" H 8100 5750 60  0001 C CNN
+	1    8100 5750
+	1    0    0    -1  
+$EndComp
+$Comp
+L complex_hierarchy_schlib:R R15
+U 1 1 4B3A1364
+P 9450 4150
+AR Path="/4B3A13A4/4B3A1364" Ref="R15"  Part="1" 
+AR Path="/4B3A1333/4B3A1364" Ref="R5"  Part="1" 
+F 0 "R15" V 9530 4150 50  0000 C CNN
+F 1 "47" V 9450 4150 50  0000 C CNN
+F 2 "Resistor_THT:R_Axial_DIN0204_L3.6mm_D1.6mm_P7.62mm_Horizontal" V 9400 4150 10  0000 C CNN
+F 3 "" H 9450 4150 60  0001 C CNN
+	1    9450 4150
+	0    1    1    0   
+$EndComp
+$Comp
+L complex_hierarchy_schlib:GND #PWR029
+U 1 1 4B3A1363
+P 10250 4550
+AR Path="/4B3A13A4/4B3A1363" Ref="#PWR029"  Part="1" 
+AR Path="/4B3A1333/4B3A1363" Ref="#PWR045"  Part="1" 
+F 0 "#PWR029" H 10250 4550 30  0001 C CNN
+F 1 "GND" H 10250 4480 30  0001 C CNN
+F 2 "" H 10250 4550 10  0001 C CNN
+F 3 "" H 10250 4550 60  0001 C CNN
+	1    10250 4550
+	1    0    0    -1  
+$EndComp
+$Comp
+L complex_hierarchy_schlib:R R21
+U 1 1 4B3A1362
+P 5250 6400
+AR Path="/4B3A13A4/4B3A1362" Ref="R21"  Part="1" 
+AR Path="/4B3A1333/4B3A1362" Ref="R11"  Part="1" 
+F 0 "R21" V 5150 6400 50  0000 C CNN
+F 1 "4,7K" V 5250 6400 50  0000 C CNN
+F 2 "Resistor_THT:R_Axial_DIN0204_L3.6mm_D1.6mm_P7.62mm_Horizontal" V 5100 6400 10  0000 C CNN
+F 3 "" H 5250 6400 60  0001 C CNN
+	1    5250 6400
+	0    1    1    0   
+$EndComp
+$Comp
+L complex_hierarchy_schlib:GND #PWR030
+U 1 1 4B3A1361
+P 5050 6400
+AR Path="/4B3A13A4/4B3A1361" Ref="#PWR030"  Part="1" 
+AR Path="/4B3A1333/4B3A1361" Ref="#PWR046"  Part="1" 
+F 0 "#PWR030" H 5050 6400 30  0001 C CNN
+F 1 "GND" H 5050 6330 30  0001 C CNN
+F 2 "" H 5050 6400 10  0001 C CNN
+F 3 "" H 5050 6400 60  0001 C CNN
+	1    5050 6400
+	0    1    1    0   
+$EndComp
+$Comp
+L complex_hierarchy_schlib:MPSA92 Q5
+U 1 1 4B3A1360
+P 7800 3300
+AR Path="/4B3A13A4/4B3A1360" Ref="Q5"  Part="1" 
+AR Path="/4B3A1333/4B3A1360" Ref="Q1"  Part="1" 
+F 0 "Q5" H 7800 3150 60  0000 R CNN
+F 1 "MPSA92" H 7800 3450 60  0000 R CNN
+F 2 "Package_TO_SOT_THT:TO-92_HandSolder" H 7750 3100 10  0000 C CNN
+F 3 "" H 7800 3300 60  0001 C CNN
+	1    7800 3300
+	1    0    0    1   
+$EndComp
+$Comp
+L complex_hierarchy_schlib:HT #PWR031
+U 1 1 4B3A135F
+P 7300 2650
+AR Path="/4B3A13A4/4B3A135F" Ref="#PWR031"  Part="1" 
+AR Path="/4B3A1333/4B3A135F" Ref="#PWR047"  Part="1" 
+F 0 "#PWR031" H 7300 2770 20  0001 C CNN
+F 1 "HT" H 7300 2740 40  0000 C CNN
+F 2 "" H 7300 2650 10  0001 C CNN
+F 3 "" H 7300 2650 60  0001 C CNN
+	1    7300 2650
+	1    0    0    -1  
+$EndComp
+$Comp
+L complex_hierarchy_schlib:HT #PWR032
+U 1 1 4B3A135E
+P 7900 2550
+AR Path="/4B3A13A4/4B3A135E" Ref="#PWR032"  Part="1" 
+AR Path="/4B3A1333/4B3A135E" Ref="#PWR048"  Part="1" 
+F 0 "#PWR032" H 7900 2670 20  0001 C CNN
+F 1 "HT" H 7900 2640 40  0000 C CNN
+F 2 "" H 7900 2550 10  0001 C CNN
+F 3 "" H 7900 2550 60  0001 C CNN
+	1    7900 2550
+	1    0    0    -1  
+$EndComp
+$Comp
+L complex_hierarchy_schlib:HT #PWR033
+U 1 1 4B3A135D
+P 8600 3300
+AR Path="/4B3A13A4/4B3A135D" Ref="#PWR033"  Part="1" 
+AR Path="/4B3A1333/4B3A135D" Ref="#PWR049"  Part="1" 
+F 0 "#PWR033" H 8600 3420 20  0001 C CNN
+F 1 "HT" H 8600 3390 40  0000 C CNN
+F 2 "" H 8600 3300 10  0001 C CNN
+F 3 "" H 8600 3300 60  0001 C CNN
+	1    8600 3300
+	1    0    0    -1  
+$EndComp
+$Comp
+L complex_hierarchy_schlib:LM358N U4
+U 2 1 4B3A135C
+P 4850 2400
+AR Path="/4B3A13A4/4B3A135C" Ref="U4"  Part="2" 
+AR Path="/4B3A1333/4B3A135C" Ref="U3"  Part="2" 
+F 0 "U4" H 4900 2600 60  0000 C CNN
+F 1 "LM358N" H 5000 2200 50  0000 C CNN
+F 2 "Package_DIP:DIP-8_W7.62mm_LongPads" H 5100 2150 10  0000 C CNN
+F 3 "" H 4850 2400 60  0001 C CNN
+	2    4850 2400
+	1    0    0    -1  
+$EndComp
+$Comp
+L complex_hierarchy_schlib:+12V #U034
+U 1 1 4B3A135B
+P 4750 1950
+AR Path="/4B3A13A4/4B3A135B" Ref="#U034"  Part="1" 
+AR Path="/4B3A1333/4B3A135B" Ref="#U050"  Part="1" 
+F 0 "#U034" H 4750 1900 20  0001 C CNN
+F 1 "+12V" H 4750 2050 40  0000 C CNN
+F 2 "" H 4750 1950 10  0001 C CNN
+F 3 "" H 4750 1950 60  0001 C CNN
+	1    4750 1950
+	1    0    0    -1  
+$EndComp
+$Comp
+L complex_hierarchy_schlib:R R17
+U 1 1 4B3A1359
+P 3950 2000
+AR Path="/4B3A13A4/4B3A1359" Ref="R17"  Part="1" 
+AR Path="/4B3A1333/4B3A1359" Ref="R7"  Part="1" 
+F 0 "R17" V 3850 2000 50  0000 C CNN
+F 1 "22K" V 3950 2000 50  0000 C CNN
+F 2 "Resistor_THT:R_Axial_DIN0204_L3.6mm_D1.6mm_P7.62mm_Horizontal" V 3800 2000 10  0000 C CNN
+F 3 "" H 3950 2000 60  0001 C CNN
+	1    3950 2000
+	0    1    1    0   
+$EndComp
+$Comp
+L complex_hierarchy_schlib:C C6
+U 1 1 4B3A1358
+P 4350 1600
+AR Path="/4B3A13A4/4B3A1358" Ref="C6"  Part="1" 
+AR Path="/4B3A1333/4B3A1358" Ref="C3"  Part="1" 
+F 0 "C6" V 4200 1600 50  0000 C CNN
+F 1 "15nF" V 4500 1600 50  0000 C CNN
+F 2 "Capacitor_THT:C_Disc_D5.0mm_W2.5mm_P5.00mm" V 4150 1600 10  0000 C CNN
+F 3 "" H 4350 1600 60  0001 C CNN
+	1    4350 1600
+	0    1    1    0   
+$EndComp
+Text Notes 2600 2950 0    80   Italic 16
+Filter:\nFc =1000Hz
+$Comp
+L complex_hierarchy_schlib:POT RV2
+U 1 1 4B3A1357
+P 5850 6400
+AR Path="/4B3A13A4/4B3A1357" Ref="RV2"  Part="1" 
+AR Path="/4B3A1333/4B3A1357" Ref="RV1"  Part="1" 
+F 0 "RV2" H 5850 6300 50  0000 C CNN
+F 1 "4,7K" H 5850 6400 50  0000 C CNN
+F 2 "Potentiometer_THT:Potentiometer_Bourns_3266W_Vertical" H 5850 6250 10  0000 C CNN
+F 3 "" H 5850 6400 60  0001 C CNN
+	1    5850 6400
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	7900 4100 7900 4400
+Wire Wire Line
+	8600 4450 8900 4450
+Wire Wire Line
+	8600 4450 8600 4600
+Wire Wire Line
+	8600 4150 9100 4150
+Wire Wire Line
+	8600 4150 8600 3900
+Wire Wire Line
+	2850 2450 2850 2400
+Wire Wire Line
+	4350 2000 4350 2200
+Wire Wire Line
+	4350 2200 4000 2200
+Wire Wire Line
+	4000 2200 4000 2400
+Connection ~ 4350 2200
+Wire Wire Line
+	4000 2750 4000 2700
+Wire Wire Line
+	4750 2850 4750 2800
+Wire Wire Line
+	4750 1950 4750 2000
+Wire Wire Line
+	7300 2700 7300 2650
+Wire Wire Line
+	7900 2550 7900 2600
+Wire Wire Line
+	7900 4800 8100 4800
+Connection ~ 7900 4800
+Wire Wire Line
+	8100 5900 8100 5950
+Wire Wire Line
+	6300 4950 6300 5000
+Wire Wire Line
+	6300 5850 6300 5800
+Wire Wire Line
+	5050 6400 5100 6400
+Wire Wire Line
+	7100 5100 7000 5100
+Wire Wire Line
+	7300 3000 7300 2900
+Wire Wire Line
+	9100 4150 9300 4150
+Wire Wire Line
+	7300 3300 7300 3450
+Wire Wire Line
+	5450 2400 5450 1600
+Wire Wire Line
+	7900 3700 7900 3900
+Wire Wire Line
+	3600 2000 3800 2000
+Wire Wire Line
+	2850 2000 3100 2000
+Wire Wire Line
+	5150 3000 5450 3000
+Wire Wire Line
+	8100 4800 8300 4800
+Wire Wire Line
+	9800 4300 9800 4450
+Wire Wire Line
+	8900 4450 9300 4450
+Wire Wire Line
+	8900 5400 8900 6400
+Wire Wire Line
+	4350 2200 4350 2300
+Wire Wire Line
+	7900 4800 7900 4900
+$EndSCHEMATC
--- a/qa/eeschema/data/netlists/complex_hierarchy/complex_hierarchy-cache.lib
+++ b/qa/eeschema/data/netlists/complex_hierarchy/complex_hierarchy-cache.lib
@ -0,0 +1,302 @@
+EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# complex_hierarchy_schlib_+12C
+#
+DEF complex_hierarchy_schlib_+12C #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "complex_hierarchy_schlib_+12C" 0 150 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 2 0 1 0 -30 50 0 100 N
+P 2 0 1 0 0 0 0 100 N
+P 2 0 1 0 0 100 30 50 N
+X +12C 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# complex_hierarchy_schlib_+12V
+#
+DEF complex_hierarchy_schlib_+12V #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "complex_hierarchy_schlib_+12V" 0 140 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 2 0 1 0 -30 50 0 100 N
+P 2 0 1 0 0 0 0 100 N
+P 2 0 1 0 0 100 30 50 N
+X +12V 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# complex_hierarchy_schlib_-VAA
+#
+DEF complex_hierarchy_schlib_-VAA #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 100 20 H I C CNN
+F1 "complex_hierarchy_schlib_-VAA" 0 100 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 3 0 1 0 0 0 0 50 0 50 N
+P 7 0 1 0 0 80 30 50 -20 50 -30 50 0 80 0 80 0 80 F
+X -VAA 1 0 0 0 U 20 20 0 0 W N
+ENDDRAW
+ENDDEF
+#
+# complex_hierarchy_schlib_7805
+#
+DEF complex_hierarchy_schlib_7805 U 0 20 Y Y 1 F N
+F0 "U" 150 -196 60 H V C CNN
+F1 "complex_hierarchy_schlib_7805" 0 200 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -200 -150 200 150 0 1 0 N
+X VO 1 400 50 200 L 30 40 1 1 w
+X GND 2 0 -250 100 U 30 40 1 1 I
+X VI 3 -400 50 200 R 30 40 1 1 I
+ENDDRAW
+ENDDEF
+#
+# complex_hierarchy_schlib_C
+#
+DEF complex_hierarchy_schlib_C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "complex_hierarchy_schlib_C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ C?
+ C_????_*
+ C_????
+ SMD*_c
+ Capacitor*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# complex_hierarchy_schlib_CONN_2
+#
+DEF complex_hierarchy_schlib_CONN_2 P 0 40 Y N 1 F N
+F0 "P" -50 0 40 V V C CNN
+F1 "complex_hierarchy_schlib_CONN_2" 50 0 40 V V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -100 150 100 -150 0 1 0 N
+X P1 1 -350 100 250 R 60 60 1 1 P I
+X PM 2 -350 -100 250 R 60 60 1 1 P I
+ENDDRAW
+ENDDEF
+#
+# complex_hierarchy_schlib_CP
+#
+DEF complex_hierarchy_schlib_CP C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "complex_hierarchy_schlib_CP" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ CP*
+ Elko*
+ TantalC*
+ C*elec
+ c_elec*
+ SMD*_Pol
+$ENDFPLIST
+DRAW
+S -90 20 -90 40 0 1 0 N
+S -90 20 90 20 0 1 0 N
+S -70 90 -30 90 0 1 0 N
+S -50 70 -50 110 0 1 0 N
+S 90 -20 -90 -40 0 1 0 F
+S 90 40 -90 40 0 1 0 N
+S 90 40 90 20 0 1 0 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# complex_hierarchy_schlib_D_Small
+#
+DEF complex_hierarchy_schlib_D_Small D 0 10 N N 1 F N
+F0 "D" -50 80 50 H V L CNN
+F1 "complex_hierarchy_schlib_D_Small" -150 -80 50 H V L CNN
+F2 "" 0 0 60 V V C CNN
+F3 "" 0 0 60 V V C CNN
+$FPLIST
+ Diode_*
+ D-Pak_TO252AA
+ *SingleDiode
+ *SingleDiode*
+ *_Diode_*
+$ENDFPLIST
+DRAW
+P 2 0 1 0 -30 -40 -30 40 N
+P 4 0 1 0 30 -40 -30 0 30 40 30 -40 F
+X K 1 -100 0 70 R 50 50 1 1 P
+X A 2 100 0 70 L 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# complex_hierarchy_schlib_GND
+#
+DEF complex_hierarchy_schlib_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "complex_hierarchy_schlib_GND" 0 -123 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 20 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# complex_hierarchy_schlib_HT
+#
+DEF complex_hierarchy_schlib_HT #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 120 50 H I C CNN
+F1 "complex_hierarchy_schlib_HT" 0 90 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 3 0 1 0 0 0 0 40 0 40 N
+P 6 0 1 0 0 40 20 20 0 70 -20 20 0 40 0 40 N
+X HT 1 0 0 0 U 20 20 0 0 W N
+ENDDRAW
+ENDDEF
+#
+# complex_hierarchy_schlib_ICL7660
+#
+DEF complex_hierarchy_schlib_ICL7660 U 0 40 Y Y 1 F N
+F0 "U" 200 400 70 H V L CNN
+F1 "complex_hierarchy_schlib_ICL7660" 50 -450 70 H V L CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -550 -350 550 350 0 1 0 N
+X CAP+ 2 -850 250 300 R 60 60 1 1 I
+X GND 3 -50 -650 300 U 60 60 1 1 W
+X CAP- 4 -850 50 300 R 60 60 1 1 I
+X VOUT 5 850 150 300 L 60 60 1 1 w
+X LV 6 850 -150 300 L 60 60 1 1 I
+X OSC 7 -850 -150 300 R 60 60 1 1 I
+X V+ 8 -50 650 300 D 60 60 1 1 W
+ENDDRAW
+ENDDEF
+#
+# complex_hierarchy_schlib_MPSA42
+#
+DEF complex_hierarchy_schlib_MPSA42 Q 0 0 Y Y 1 F N
+F0 "Q" 150 -150 60 H V L CNN
+F1 "complex_hierarchy_schlib_MPSA42" 150 150 60 H V L CNN
+F2 "TO92-CBE" 150 0 30 H I C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ TO92-CBE
+$ENDFPLIST
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 0 0 100 100 N
+P 3 0 1 10 0 75 0 -75 0 -75 N
+P 3 0 1 0 50 -50 0 0 0 0 N
+P 3 0 1 0 90 -90 100 -100 100 -100 N
+P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F
+X E 1 100 -200 100 U 20 20 1 1 P
+X B 2 -200 0 200 R 20 20 1 1 I
+X C 3 100 200 100 D 20 20 1 1 P
+ENDDRAW
+ENDDEF
+#
+# complex_hierarchy_schlib_MPSA92
+#
+DEF complex_hierarchy_schlib_MPSA92 Q 0 0 Y Y 1 F N
+F0 "Q" 150 -150 60 H V L CNN
+F1 "complex_hierarchy_schlib_MPSA92" 150 150 60 H V L CNN
+F2 "TO92-CBE" 150 0 30 H I C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ TO92-CBE
+$ENDFPLIST
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 0 0 100 100 N
+P 3 0 1 10 0 75 0 -75 0 -75 F
+P 3 0 1 0 25 -25 0 0 0 0 N
+P 3 0 1 0 100 -100 65 -65 65 -65 N
+P 5 0 1 0 25 -25 50 -75 75 -50 25 -25 25 -25 F
+X E 1 100 -200 100 U 20 20 1 1 P
+X B 2 -200 0 200 R 20 20 1 1 I
+X C 3 100 200 100 D 20 20 1 1 P
+ENDDRAW
+ENDDEF
+#
+# complex_hierarchy_schlib_POT
+#
+DEF complex_hierarchy_schlib_POT RV 0 40 Y N 1 F N
+F0 "RV" 0 -100 50 H V C CNN
+F1 "complex_hierarchy_schlib_POT" 0 0 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -150 50 150 -50 0 1 0 N
+P 3 0 1 0 0 50 -20 70 20 70 F
+X 1 1 -250 0 100 R 40 40 1 1 P
+X 2 2 0 150 80 D 40 40 1 1 P
+X 3 3 250 0 100 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# complex_hierarchy_schlib_PWR_FLAG
+#
+DEF complex_hierarchy_schlib_PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 95 50 H I C CNN
+F1 "complex_hierarchy_schlib_PWR_FLAG" 0 180 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N
+X pwr 1 0 0 0 U 20 20 0 0 w
+ENDDRAW
+ENDDEF
+#
+# complex_hierarchy_schlib_R
+#
+DEF complex_hierarchy_schlib_R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "complex_hierarchy_schlib_R" 0 0 50 V V C CNN
+F2 "" -70 0 30 V V C CNN
+F3 "" 0 0 30 H V C CNN
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S -40 -100 40 100 0 1 10 N
+X ~ 1 0 150 50 D 60 60 1 1 P
+X ~ 2 0 -150 50 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# complex_hierarchy_schlib_VCC
+#
+DEF complex_hierarchy_schlib_VCC #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "complex_hierarchy_schlib_VCC" 0 150 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 75 25 0 1 0 N
+P 2 0 1 0 0 0 0 50 N
+X VCC 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+#End Library
--- a/qa/eeschema/data/netlists/complex_hierarchy/complex_hierarchy.net
+++ b/qa/eeschema/data/netlists/complex_hierarchy/complex_hierarchy.net
@ -0,0 +1,803 @@
+(export (version "D")
+  (design
+    (source "/home/jon/work/kicad-master/qa/eeschema/data/netlists/complex_hierarchy/complex_hierarchy.sch")
+    (date "Sun 19 Apr 2020 16:13:41 EDT")
+    (tool "Eeschema (5.99.0-1347-g0d2b30b74-dirty)")
+    (sheet (number "1") (name "/") (tstamps "/")
+      (title_block
+        (title "Complex hierarchy: demo")
+        (company)
+        (rev)
+        (date "2017-01-15")
+        (source "complex_hierarchy.sch")
+        (comment (number "1") (value ""))
+        (comment (number "2") (value ""))
+        (comment (number "3") (value ""))
+        (comment (number "4") (value ""))
+        (comment (number "5") (value ""))
+        (comment (number "6") (value ""))
+        (comment (number "7") (value ""))
+        (comment (number "8") (value ""))
+        (comment (number "9") (value ""))))
+    (sheet (number "2") (name "/ampli_ht_vertical/") (tstamps "/00000000-0000-0000-0000-00004b3a1333/")
+      (title_block
+        (title "Complex hierarchy: demo")
+        (company)
+        (rev "1")
+        (date "2017-01-15")
+        (source "ampli_ht.sch")
+        (comment (number "1") (value ""))
+        (comment (number "2") (value ""))
+        (comment (number "3") (value ""))
+        (comment (number "4") (value ""))
+        (comment (number "5") (value ""))
+        (comment (number "6") (value ""))
+        (comment (number "7") (value ""))
+        (comment (number "8") (value ""))
+        (comment (number "9") (value ""))))
+    (sheet (number "3") (name "/ampli_ht_horizontal/") (tstamps "/00000000-0000-0000-0000-00004b3a13a4/")
+      (title_block
+        (title "Complex hierarchy: demo")
+        (company)
+        (rev "1")
+        (date "2017-01-15")
+        (source "ampli_ht.sch")
+        (comment (number "1") (value ""))
+        (comment (number "2") (value ""))
+        (comment (number "3") (value ""))
+        (comment (number "4") (value ""))
+        (comment (number "5") (value ""))
+        (comment (number "6") (value ""))
+        (comment (number "7") (value ""))
+        (comment (number "8") (value ""))
+        (comment (number "9") (value "")))))
+  (components
+    (comp (ref "C1")
+      (value "47uF")
+      (footprint "Capacitor_THT:CP_Axial_L10.0mm_D4.5mm_P15.00mm_Horizontal")
+      (libsource (lib "complex_hierarchy_schlib") (part "CP") (description ""))
+      (sheetpath (names "/") (tstamps "/"))
+      (tstamp "00000000-0000-0000-0000-00004b03cec2"))
+    (comp (ref "C10")
+      (value "10uF")
+      (footprint "Capacitor_THT:CP_Axial_L10.0mm_D4.5mm_P15.00mm_Horizontal")
+      (libsource (lib "complex_hierarchy_schlib") (part "CP") (description ""))
+      (sheetpath (names "/") (tstamps "/"))
+      (tstamp "00000000-0000-0000-0000-00004b4b15e7"))
+    (comp (ref "C11")
+      (value "10uF")
+      (footprint "Capacitor_THT:CP_Axial_L10.0mm_D4.5mm_P15.00mm_Horizontal")
+      (libsource (lib "complex_hierarchy_schlib") (part "CP") (description ""))
+      (sheetpath (names "/") (tstamps "/"))
+      (tstamp "00000000-0000-0000-0000-00004b4b15d9"))
+    (comp (ref "C2")
+      (value "47uF/20V")
+      (footprint "Capacitor_THT:CP_Axial_L10.0mm_D4.5mm_P15.00mm_Horizontal")
+      (libsource (lib "complex_hierarchy_schlib") (part "CP") (description ""))
+      (sheetpath (names "/") (tstamps "/"))
+      (tstamp "00000000-0000-0000-0000-00004ae173cf"))
+    (comp (ref "C9")
+      (value "47uF/63V")
+      (footprint "Capacitor_THT:CP_Axial_L11.0mm_D6.0mm_P18.00mm_Horizontal")
+      (libsource (lib "complex_hierarchy_schlib") (part "CP") (description ""))
+      (sheetpath (names "/") (tstamps "/"))
+      (tstamp "00000000-0000-0000-0000-00004b3a1558"))
+    (comp (ref "D1")
+      (value "1N4007")
+      (footprint "Diode_THT:D_DO-41_SOD81_P12.70mm_Horizontal")
+      (libsource (lib "complex_hierarchy_schlib") (part "D_Small") (description ""))
+      (sheetpath (names "/") (tstamps "/"))
+      (tstamp "00000000-0000-0000-0000-00004ae172f4"))
+    (comp (ref "P1")
+      (value "CONN_2")
+      (footprint "TerminalBlock_Altech:Altech_AK300_1x02_P5.00mm_45-Degree")
+      (libsource (lib "complex_hierarchy_schlib") (part "CONN_2") (description ""))
+      (sheetpath (names "/") (tstamps "/"))
+      (tstamp "00000000-0000-0000-0000-00004b3a12f4"))
+    (comp (ref "P2")
+      (value "CONN_2")
+      (footprint "TerminalBlock_Altech:Altech_AK300_1x02_P5.00mm_45-Degree")
+      (libsource (lib "complex_hierarchy_schlib") (part "CONN_2") (description ""))
+      (sheetpath (names "/") (tstamps "/"))
+      (tstamp "00000000-0000-0000-0000-00004ad71b06"))
+    (comp (ref "U1")
+      (value "ICL7660")
+      (footprint "Package_DIP:DIP-8_W7.62mm_LongPads")
+      (libsource (lib "complex_hierarchy_schlib") (part "ICL7660") (description ""))
+      (sheetpath (names "/") (tstamps "/"))
+      (tstamp "00000000-0000-0000-0000-00004b4b1230"))
+    (comp (ref "U2")
+      (value "78L05")
+      (footprint "Package_TO_SOT_THT:TO-92_HandSolder")
+      (libsource (lib "complex_hierarchy_schlib") (part "7805") (description ""))
+      (sheetpath (names "/") (tstamps "/"))
+      (tstamp "00000000-0000-0000-0000-00004b4b1532"))
+    (comp (ref "C12")
+      (value "150nF")
+      (footprint "Capacitor_THT:C_Disc_D5.0mm_W2.5mm_P5.00mm")
+      (libsource (lib "complex_hierarchy_schlib") (part "C") (description ""))
+      (sheetpath (names "/ampli_ht_vertical/") (tstamps "/00000000-0000-0000-0000-00004b3a1333/"))
+      (tstamp "00000000-0000-0000-0000-00004b4f3641"))
+    (comp (ref "C3")
+      (value "15nF")
+      (footprint "Capacitor_THT:C_Disc_D5.0mm_W2.5mm_P5.00mm")
+      (libsource (lib "complex_hierarchy_schlib") (part "C") (description ""))
+      (sheetpath (names "/ampli_ht_vertical/") (tstamps "/00000000-0000-0000-0000-00004b3a1333/"))
+      (tstamp "00000000-0000-0000-0000-00004b3a1358"))
+    (comp (ref "C4")
+      (value "4.7nF")
+      (footprint "Capacitor_THT:C_Disc_D5.0mm_W2.5mm_P5.00mm")
+      (libsource (lib "complex_hierarchy_schlib") (part "C") (description ""))
+      (sheetpath (names "/ampli_ht_vertical/") (tstamps "/00000000-0000-0000-0000-00004b3a1333/"))
+      (tstamp "00000000-0000-0000-0000-00004b3a1366"))
+    (comp (ref "C5")
+      (value "820pF")
+      (footprint "Capacitor_THT:C_Disc_D5.0mm_W2.5mm_P5.00mm")
+      (libsource (lib "complex_hierarchy_schlib") (part "C") (description ""))
+      (sheetpath (names "/ampli_ht_vertical/") (tstamps "/00000000-0000-0000-0000-00004b3a1333/"))
+      (tstamp "00000000-0000-0000-0000-00004b3a1365"))
+    (comp (ref "D2")
+      (value "1N4148")
+      (footprint "Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal")
+      (libsource (lib "complex_hierarchy_schlib") (part "D_Small") (description ""))
+      (sheetpath (names "/ampli_ht_vertical/") (tstamps "/00000000-0000-0000-0000-00004b3a1333/"))
+      (tstamp "00000000-0000-0000-0000-00004b3a1375"))
+    (comp (ref "D3")
+      (value "1N4148")
+      (footprint "Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal")
+      (libsource (lib "complex_hierarchy_schlib") (part "D_Small") (description ""))
+      (sheetpath (names "/ampli_ht_vertical/") (tstamps "/00000000-0000-0000-0000-00004b3a1333/"))
+      (tstamp "00000000-0000-0000-0000-00004b3a1377"))
+    (comp (ref "D4")
+      (value "1N4148")
+      (footprint "Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal")
+      (libsource (lib "complex_hierarchy_schlib") (part "D_Small") (description ""))
+      (sheetpath (names "/ampli_ht_vertical/") (tstamps "/00000000-0000-0000-0000-00004b3a1333/"))
+      (tstamp "00000000-0000-0000-0000-00004b3a137b"))
+    (comp (ref "D8")
+      (value "1N4148")
+      (footprint "Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal")
+      (libsource (lib "complex_hierarchy_schlib") (part "D_Small") (description ""))
+      (sheetpath (names "/ampli_ht_vertical/") (tstamps "/00000000-0000-0000-0000-00004b3a1333/"))
+      (tstamp "00000000-0000-0000-0000-00004b616afa"))
+    (comp (ref "P3")
+      (value "CONN_2")
+      (footprint "TerminalBlock_Altech:Altech_AK300_1x02_P5.00mm_45-Degree")
+      (libsource (lib "complex_hierarchy_schlib") (part "CONN_2") (description ""))
+      (sheetpath (names "/ampli_ht_vertical/") (tstamps "/00000000-0000-0000-0000-00004b3a1333/"))
+      (tstamp "00000000-0000-0000-0000-00004b3a136c"))
+    (comp (ref "P4")
+      (value "CONN_2")
+      (footprint "TerminalBlock_Altech:Altech_AK300_1x02_P5.00mm_45-Degree")
+      (libsource (lib "complex_hierarchy_schlib") (part "CONN_2") (description ""))
+      (sheetpath (names "/ampli_ht_vertical/") (tstamps "/00000000-0000-0000-0000-00004b3a1333/"))
+      (tstamp "00000000-0000-0000-0000-00004b3a1367"))
+    (comp (ref "Q1")
+      (value "MPSA92")
+      (footprint "Package_TO_SOT_THT:TO-92_HandSolder")
+      (libsource (lib "complex_hierarchy_schlib") (part "MPSA92") (description ""))
+      (sheetpath (names "/ampli_ht_vertical/") (tstamps "/00000000-0000-0000-0000-00004b3a1333/"))
+      (tstamp "00000000-0000-0000-0000-00004b3a1360"))
+    (comp (ref "Q2")
+      (value "MPSA42")
+      (footprint "Package_TO_SOT_THT:TO-92_HandSolder")
+      (libsource (lib "complex_hierarchy_schlib") (part "MPSA42") (description ""))
+      (sheetpath (names "/ampli_ht_vertical/") (tstamps "/00000000-0000-0000-0000-00004b3a1333/"))
+      (tstamp "00000000-0000-0000-0000-00004b3a137d"))
+    (comp (ref "Q3")
+      (value "MPSA92")
+      (footprint "Package_TO_SOT_THT:TO-92_HandSolder")
+      (libsource (lib "complex_hierarchy_schlib") (part "MPSA92") (description ""))
+      (sheetpath (names "/ampli_ht_vertical/") (tstamps "/00000000-0000-0000-0000-00004b3a1333/"))
+      (tstamp "00000000-0000-0000-0000-00004b3a137c"))
+    (comp (ref "Q4")
+      (value "MPSA42")
+      (footprint "Package_TO_SOT_THT:TO-92_HandSolder")
+      (libsource (lib "complex_hierarchy_schlib") (part "MPSA42") (description ""))
+      (sheetpath (names "/ampli_ht_vertical/") (tstamps "/00000000-0000-0000-0000-00004b3a1333/"))
+      (tstamp "00000000-0000-0000-0000-00004b3a1379"))
+    (comp (ref "R3")
+      (value "470")
+      (footprint "Resistor_THT:R_Axial_DIN0204_L3.6mm_D1.6mm_P7.62mm_Horizontal")
+      (libsource (lib "complex_hierarchy_schlib") (part "R") (description ""))
+      (sheetpath (names "/ampli_ht_vertical/") (tstamps "/00000000-0000-0000-0000-00004b3a1333/"))
+      (tstamp "00000000-0000-0000-0000-00004b3a1376"))
+    (comp (ref "R4")
+      (value "220K")
+      (footprint "Resistor_THT:R_Axial_DIN0204_L3.6mm_D1.6mm_P7.62mm_Horizontal")
+      (libsource (lib "complex_hierarchy_schlib") (part "R") (description ""))
+      (sheetpath (names "/ampli_ht_vertical/") (tstamps "/00000000-0000-0000-0000-00004b3a1333/"))
+      (tstamp "00000000-0000-0000-0000-00004b3a1374"))
+    (comp (ref "R5")
+      (value "47")
+      (footprint "Resistor_THT:R_Axial_DIN0204_L3.6mm_D1.6mm_P7.62mm_Horizontal")
+      (libsource (lib "complex_hierarchy_schlib") (part "R") (description ""))
+      (sheetpath (names "/ampli_ht_vertical/") (tstamps "/00000000-0000-0000-0000-00004b3a1333/"))
+      (tstamp "00000000-0000-0000-0000-00004b3a1364"))
+    (comp (ref "R6")
+      (value "22K")
+      (footprint "Resistor_THT:R_Axial_DIN0204_L3.6mm_D1.6mm_P7.62mm_Horizontal")
+      (libsource (lib "complex_hierarchy_schlib") (part "R") (description ""))
+      (sheetpath (names "/ampli_ht_vertical/") (tstamps "/00000000-0000-0000-0000-00004b3a1333/"))
+      (tstamp "00000000-0000-0000-0000-00004b3a136b"))
+    (comp (ref "R7")
+      (value "22K")
+      (footprint "Resistor_THT:R_Axial_DIN0204_L3.6mm_D1.6mm_P7.62mm_Horizontal")
+      (libsource (lib "complex_hierarchy_schlib") (part "R") (description ""))
+      (sheetpath (names "/ampli_ht_vertical/") (tstamps "/00000000-0000-0000-0000-00004b3a1333/"))
+      (tstamp "00000000-0000-0000-0000-00004b3a1359"))
+    (comp (ref "R8")
+      (value "1K")
+      (footprint "Resistor_THT:R_Axial_DIN0204_L3.6mm_D1.6mm_P7.62mm_Horizontal")
+      (libsource (lib "complex_hierarchy_schlib") (part "R") (description ""))
+      (sheetpath (names "/ampli_ht_vertical/") (tstamps "/00000000-0000-0000-0000-00004b3a1333/"))
+      (tstamp "00000000-0000-0000-0000-00004b3a1371"))
+    (comp (ref "R9")
+      (value "1K")
+      (footprint "Resistor_THT:R_Axial_DIN0204_L3.6mm_D1.6mm_P7.62mm_Horizontal")
+      (libsource (lib "complex_hierarchy_schlib") (part "R") (description ""))
+      (sheetpath (names "/ampli_ht_vertical/") (tstamps "/00000000-0000-0000-0000-00004b3a1333/"))
+      (tstamp "00000000-0000-0000-0000-00004b3a136d"))
+    (comp (ref "R10")
+      (value "5,6K")
+      (footprint "Resistor_THT:R_Axial_DIN0204_L3.6mm_D1.6mm_P7.62mm_Horizontal")
+      (libsource (lib "complex_hierarchy_schlib") (part "R") (description ""))
+      (sheetpath (names "/ampli_ht_vertical/") (tstamps "/00000000-0000-0000-0000-00004b3a1333/"))
+      (tstamp "00000000-0000-0000-0000-00004b61688c"))
+    (comp (ref "R11")
+      (value "4,7K")
+      (footprint "Resistor_THT:R_Axial_DIN0204_L3.6mm_D1.6mm_P7.62mm_Horizontal")
+      (libsource (lib "complex_hierarchy_schlib") (part "R") (description ""))
+      (sheetpath (names "/ampli_ht_vertical/") (tstamps "/00000000-0000-0000-0000-00004b3a1333/"))
+      (tstamp "00000000-0000-0000-0000-00004b3a1362"))
+    (comp (ref "R12")
+      (value "220K")
+      (footprint "Resistor_THT:R_Axial_DIN0204_L3.6mm_D1.6mm_P7.62mm_Horizontal")
+      (libsource (lib "complex_hierarchy_schlib") (part "R") (description ""))
+      (sheetpath (names "/ampli_ht_vertical/") (tstamps "/00000000-0000-0000-0000-00004b3a1333/"))
+      (tstamp "00000000-0000-0000-0000-00004b3a1370"))
+    (comp (ref "R23")
+      (value "1K")
+      (footprint "Resistor_THT:R_Axial_DIN0204_L3.6mm_D1.6mm_P7.62mm_Horizontal")
+      (libsource (lib "complex_hierarchy_schlib") (part "R") (description ""))
+      (sheetpath (names "/ampli_ht_vertical/") (tstamps "/00000000-0000-0000-0000-00004b3a1333/"))
+      (tstamp "00000000-0000-0000-0000-00004b4f363e"))
+    (comp (ref "R25")
+      (value "47")
+      (footprint "Resistor_THT:R_Axial_DIN0204_L3.6mm_D1.6mm_P7.62mm_Horizontal")
+      (libsource (lib "complex_hierarchy_schlib") (part "R") (description ""))
+      (sheetpath (names "/ampli_ht_vertical/") (tstamps "/00000000-0000-0000-0000-00004b3a1333/"))
+      (tstamp "00000000-0000-0000-0000-00004b616b96"))
+    (comp (ref "R26")
+      (value "220K")
+      (footprint "Resistor_THT:R_Axial_DIN0204_L3.6mm_D1.6mm_P7.62mm_Horizontal")
+      (libsource (lib "complex_hierarchy_schlib") (part "R") (description ""))
+      (sheetpath (names "/ampli_ht_vertical/") (tstamps "/00000000-0000-0000-0000-00004b3a1333/"))
+      (tstamp "00000000-0000-0000-0000-00004b617b88"))
+    (comp (ref "RV1")
+      (value "4,7K")
+      (footprint "Potentiometer_THT:Potentiometer_Bourns_3266W_Vertical")
+      (libsource (lib "complex_hierarchy_schlib") (part "POT") (description ""))
+      (sheetpath (names "/ampli_ht_vertical/") (tstamps "/00000000-0000-0000-0000-00004b3a1333/"))
+      (tstamp "00000000-0000-0000-0000-00004b3a1357"))
+    (comp (ref "U3")
+      (value "LM358N")
+      (footprint "Package_DIP:DIP-8_W7.62mm_LongPads")
+      (libsource (lib "") (part "LM358N") (description ""))
+      (sheetpath (names "/ampli_ht_vertical/") (tstamps "/00000000-0000-0000-0000-00004b3a1333/"))
+      (tstamp "00000000-0000-0000-0000-00004b3a1368"))
+    (comp (ref "C14")
+      (value "150nF")
+      (footprint "Capacitor_THT:C_Disc_D5.0mm_W2.5mm_P5.00mm")
+      (libsource (lib "complex_hierarchy_schlib") (part "C") (description ""))
+      (sheetpath (names "/ampli_ht_horizontal/") (tstamps "/00000000-0000-0000-0000-00004b3a13a4/"))
+      (tstamp "00000000-0000-0000-0000-00004b4f3641"))
+    (comp (ref "C6")
+      (value "15nF")
+      (footprint "Capacitor_THT:C_Disc_D5.0mm_W2.5mm_P5.00mm")
+      (libsource (lib "complex_hierarchy_schlib") (part "C") (description ""))
+      (sheetpath (names "/ampli_ht_horizontal/") (tstamps "/00000000-0000-0000-0000-00004b3a13a4/"))
+      (tstamp "00000000-0000-0000-0000-00004b3a1358"))
+    (comp (ref "C7")
+      (value "4.7nF")
+      (footprint "Capacitor_THT:C_Disc_D5.0mm_W2.5mm_P5.00mm")
+      (libsource (lib "complex_hierarchy_schlib") (part "C") (description ""))
+      (sheetpath (names "/ampli_ht_horizontal/") (tstamps "/00000000-0000-0000-0000-00004b3a13a4/"))
+      (tstamp "00000000-0000-0000-0000-00004b3a1366"))
+    (comp (ref "C8")
+      (value "820pF")
+      (footprint "Capacitor_THT:C_Disc_D5.0mm_W2.5mm_P5.00mm")
+      (libsource (lib "complex_hierarchy_schlib") (part "C") (description ""))
+      (sheetpath (names "/ampli_ht_horizontal/") (tstamps "/00000000-0000-0000-0000-00004b3a13a4/"))
+      (tstamp "00000000-0000-0000-0000-00004b3a1365"))
+    (comp (ref "D5")
+      (value "1N4148")
+      (footprint "Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal")
+      (libsource (lib "complex_hierarchy_schlib") (part "D_Small") (description ""))
+      (sheetpath (names "/ampli_ht_horizontal/") (tstamps "/00000000-0000-0000-0000-00004b3a13a4/"))
+      (tstamp "00000000-0000-0000-0000-00004b3a1375"))
+    (comp (ref "D6")
+      (value "1N4148")
+      (footprint "Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal")
+      (libsource (lib "complex_hierarchy_schlib") (part "D_Small") (description ""))
+      (sheetpath (names "/ampli_ht_horizontal/") (tstamps "/00000000-0000-0000-0000-00004b3a13a4/"))
+      (tstamp "00000000-0000-0000-0000-00004b3a1377"))
+    (comp (ref "D7")
+      (value "1N4148")
+      (footprint "Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal")
+      (libsource (lib "complex_hierarchy_schlib") (part "D_Small") (description ""))
+      (sheetpath (names "/ampli_ht_horizontal/") (tstamps "/00000000-0000-0000-0000-00004b3a13a4/"))
+      (tstamp "00000000-0000-0000-0000-00004b3a137b"))
+    (comp (ref "D9")
+      (value "1N4148")
+      (footprint "Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal")
+      (libsource (lib "complex_hierarchy_schlib") (part "D_Small") (description ""))
+      (sheetpath (names "/ampli_ht_horizontal/") (tstamps "/00000000-0000-0000-0000-00004b3a13a4/"))
+      (tstamp "00000000-0000-0000-0000-00004b616afa"))
+    (comp (ref "P5")
+      (value "CONN_2")
+      (footprint "TerminalBlock_Altech:Altech_AK300_1x02_P5.00mm_45-Degree")
+      (libsource (lib "complex_hierarchy_schlib") (part "CONN_2") (description ""))
+      (sheetpath (names "/ampli_ht_horizontal/") (tstamps "/00000000-0000-0000-0000-00004b3a13a4/"))
+      (tstamp "00000000-0000-0000-0000-00004b3a136c"))
+    (comp (ref "P6")
+      (value "CONN_2")
+      (footprint "TerminalBlock_Altech:Altech_AK300_1x02_P5.00mm_45-Degree")
+      (libsource (lib "complex_hierarchy_schlib") (part "CONN_2") (description ""))
+      (sheetpath (names "/ampli_ht_horizontal/") (tstamps "/00000000-0000-0000-0000-00004b3a13a4/"))
+      (tstamp "00000000-0000-0000-0000-00004b3a1367"))
+    (comp (ref "Q5")
+      (value "MPSA92")
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+      (tstamp "00000000-0000-0000-0000-00004b61688c"))
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+      (sheetpath (names "/ampli_ht_horizontal/") (tstamps "/00000000-0000-0000-0000-00004b3a13a4/"))
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+      (libsource (lib "complex_hierarchy_schlib") (part "R") (description ""))
+      (sheetpath (names "/ampli_ht_horizontal/") (tstamps "/00000000-0000-0000-0000-00004b3a13a4/"))
+      (tstamp "00000000-0000-0000-0000-00004b617b88"))
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+      (tstamp "00000000-0000-0000-0000-00004b3a1357"))
+    (comp (ref "U4")
+      (value "LM358N")
+      (footprint "Package_DIP:DIP-8_W7.62mm_LongPads")
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+      (sheetpath (names "/ampli_ht_horizontal/") (tstamps "/00000000-0000-0000-0000-00004b3a13a4/"))
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+        (pin (num "3") (name "+") (type "input"))
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+        (pin (num "5") (name "+") (type "input"))
+        (pin (num "6") (name "-") (type "input"))
+        (pin (num "7") (name "~") (type "output"))
+        (pin (num "8") (name "V+") (type "power_in"))))
+    (libpart (lib "complex_hierarchy_schlib") (part "7805")
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+        (field (name "Value") "7805"))
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+        (pin (num "2") (name "GND") (type "input"))
+        (pin (num "3") (name "VI") (type "input"))))
+    (libpart (lib "complex_hierarchy_schlib") (part "C")
+      (footprints
+        (fp "C?")
+        (fp "C_????_*")
+        (fp "C_????")
+        (fp "SMD*_c")
+        (fp "Capacitor*"))
+      (fields
+        (field (name "Reference") "C")
+        (field (name "Value") "C"))
+      (pins
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+        (pin (num "2") (name "~") (type "passive"))))
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+        (pin (num "2") (name "PM") (type "passive"))))
+    (libpart (lib "complex_hierarchy_schlib") (part "CP")
+      (footprints
+        (fp "CP*")
+        (fp "Elko*")
+        (fp "TantalC*")
+        (fp "C*elec")
+        (fp "c_elec*")
+        (fp "SMD*_Pol"))
+      (fields
+        (field (name "Reference") "C")
+        (field (name "Value") "CP"))
+      (pins
+        (pin (num "1") (name "~") (type "passive"))
+        (pin (num "2") (name "~") (type "passive"))))
+    (libpart (lib "complex_hierarchy_schlib") (part "D_Small")
+      (footprints
+        (fp "Diode_*")
+        (fp "D-Pak_TO252AA")
+        (fp "*SingleDiode")
+        (fp "*SingleDiode*")
+        (fp "*_Diode_*"))
+      (fields
+        (field (name "Reference") "D")
+        (field (name "Value") "D_Small"))
+      (pins
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+        (pin (num "2") (name "A") (type "passive"))))
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+        (pin (num "3") (name "GND") (type "power_in"))
+        (pin (num "4") (name "CAP-") (type "input"))
+        (pin (num "5") (name "VOUT") (type "power_out"))
+        (pin (num "6") (name "LV") (type "input"))
+        (pin (num "7") (name "OSC") (type "input"))
+        (pin (num "8") (name "V+") (type "power_in"))))
+    (libpart (lib "complex_hierarchy_schlib") (part "MPSA42")
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+        (field (name "Footprint") "TO92-CBE"))
+      (pins
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+        (pin (num "2") (name "B") (type "input"))
+        (pin (num "3") (name "C") (type "passive"))))
+    (libpart (lib "complex_hierarchy_schlib") (part "MPSA92")
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+      (pins
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+        (pin (num "2") (name "B") (type "input"))
+        (pin (num "3") (name "C") (type "passive"))))
+    (libpart (lib "complex_hierarchy_schlib") (part "POT")
+      (fields
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+        (field (name "Value") "POT"))
+      (pins
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+        (pin (num "2") (name "2") (type "passive"))
+        (pin (num "3") (name "3") (type "passive"))))
+    (libpart (lib "complex_hierarchy_schlib") (part "R")
+      (footprints
+        (fp "R_*")
+        (fp "Resistor_*"))
+      (fields
+        (field (name "Reference") "R")
+        (field (name "Value") "R"))
+      (pins
+        (pin (num "1") (name "~") (type "passive"))
+        (pin (num "2") (name "~") (type "passive")))))
+  (libraries
+    (library (logical "complex_hierarchy_schlib")
+      (uri "/home/jon/work/kicad-master/qa/eeschema/data/netlists/complex_hierarchy/complex_hierarchy_schlib.lib")))
+  (nets
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+      (node (ref "C2") (pin "1"))
+      (node (ref "D1") (pin "1") (pinfunction "K"))
+      (node (ref "U2") (pin "3") (pinfunction "VI"))
+      (node (ref "U3") (pin "8") (pinfunction "V+"))
+      (node (ref "U4") (pin "8") (pinfunction "V+")))
+    (net (code "2") (name "-VAA")
+      (node (ref "C11") (pin "2"))
+      (node (ref "U1") (pin "5") (pinfunction "VOUT"))
+      (node (ref "U3") (pin "4") (pinfunction "V-"))
+      (node (ref "U4") (pin "4") (pinfunction "V-")))
+    (net (code "3") (name "/12Vext")
+      (node (ref "D1") (pin "2") (pinfunction "A"))
+      (node (ref "P2") (pin "1") (pinfunction "P1")))
+    (net (code "4") (name "/ampli_ht_horizontal/PIEZO_IN")
+      (node (ref "P6") (pin "1") (pinfunction "P1"))
+      (node (ref "R24") (pin "2")))
+    (net (code "5") (name "/ampli_ht_horizontal/PIEZO_OUT")
+      (node (ref "P5") (pin "1") (pinfunction "P1"))
+      (node (ref "R15") (pin "1"))
+      (node (ref "R27") (pin "1")))
+    (net (code "6") (name "/ampli_ht_horizontal/S_OUT+")
+      (node (ref "R22") (pin "1"))
+      (node (ref "R28") (pin "1"))
+      (node (ref "RV2") (pin "3") (pinfunction "3")))
+    (net (code "7") (name "/ampli_ht_horizontal/Vpil_0_3,3V")
+      (node (ref "C6") (pin "1"))
+      (node (ref "U4") (pin "3") (pinfunction "+"))
+      (node (ref "U4") (pin "6") (pinfunction "-"))
+      (node (ref "U4") (pin "7")))
+    (net (code "8") (name "/ampli_ht_vertical/PIEZO_IN")
+      (node (ref "P4") (pin "1") (pinfunction "P1"))
+      (node (ref "R23") (pin "2")))
+    (net (code "9") (name "/ampli_ht_vertical/PIEZO_OUT")
+      (node (ref "P3") (pin "1") (pinfunction "P1"))
+      (node (ref "R25") (pin "1"))
+      (node (ref "R5") (pin "1")))
+    (net (code "10") (name "/ampli_ht_vertical/S_OUT+")
+      (node (ref "R12") (pin "1"))
+      (node (ref "R26") (pin "1"))
+      (node (ref "RV1") (pin "3") (pinfunction "3")))
+    (net (code "11") (name "/ampli_ht_vertical/Vpil_0_3,3V")
+      (node (ref "C3") (pin "1"))
+      (node (ref "U3") (pin "3") (pinfunction "+"))
+      (node (ref "U3") (pin "6") (pinfunction "-"))
+      (node (ref "U3") (pin "7")))
+    (net (code "12") (name "GND")
+      (node (ref "C1") (pin "2"))
+      (node (ref "C11") (pin "1"))
+      (node (ref "C12") (pin "2"))
+      (node (ref "C14") (pin "2"))
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+      (node (ref "C7") (pin "2"))
+      (node (ref "C8") (pin "2"))
+      (node (ref "C9") (pin "2"))
+      (node (ref "P1") (pin "2") (pinfunction "PM"))
+      (node (ref "P2") (pin "2") (pinfunction "PM"))
+      (node (ref "P3") (pin "2") (pinfunction "PM"))
+      (node (ref "P4") (pin "2") (pinfunction "PM"))
+      (node (ref "P5") (pin "2") (pinfunction "PM"))
+      (node (ref "P6") (pin "2") (pinfunction "PM"))
+      (node (ref "Q3") (pin "3") (pinfunction "C"))
+      (node (ref "Q7") (pin "3") (pinfunction "C"))
+      (node (ref "R11") (pin "2"))
+      (node (ref "R14") (pin "2"))
+      (node (ref "R18") (pin "2"))
+      (node (ref "R21") (pin "2"))
+      (node (ref "R4") (pin "2"))
+      (node (ref "R8") (pin "2"))
+      (node (ref "U1") (pin "3") (pinfunction "GND"))
+      (node (ref "U2") (pin "2") (pinfunction "GND")))
+    (net (code "13") (name "HT")
+      (node (ref "C9") (pin "1"))
+      (node (ref "D2") (pin "2") (pinfunction "A"))
+      (node (ref "D5") (pin "2") (pinfunction "A"))
+      (node (ref "P1") (pin "1") (pinfunction "P1"))
+      (node (ref "Q2") (pin "3") (pinfunction "C"))
+      (node (ref "Q6") (pin "3") (pinfunction "C"))
+      (node (ref "R13") (pin "1"))
+      (node (ref "R3") (pin "1")))
+    (net (code "14") (name "Net-(C10-Pad1)")
+      (node (ref "C10") (pin "1"))
+      (node (ref "U1") (pin "2") (pinfunction "CAP+")))
+    (net (code "15") (name "Net-(C10-Pad2)")
+      (node (ref "C10") (pin "2"))
+      (node (ref "U1") (pin "4") (pinfunction "CAP-")))
+    (net (code "16") (name "Net-(C12-Pad1)")
+      (node (ref "C12") (pin "1"))
+      (node (ref "R23") (pin "1"))
+      (node (ref "R6") (pin "2")))
+    (net (code "17") (name "Net-(C14-Pad1)")
+      (node (ref "C14") (pin "1"))
+      (node (ref "R16") (pin "2"))
+      (node (ref "R24") (pin "1")))
+    (net (code "18") (name "Net-(C3-Pad2)")
+      (node (ref "C3") (pin "2"))
+      (node (ref "R6") (pin "1"))
+      (node (ref "R7") (pin "2")))
+    (net (code "19") (name "Net-(C4-Pad1)")
+      (node (ref "C4") (pin "1"))
+      (node (ref "R7") (pin "1"))
+      (node (ref "U3") (pin "5") (pinfunction "+")))
+    (net (code "20") (name "Net-(C5-Pad1)")
+      (node (ref "C5") (pin "1"))
+      (node (ref "R10") (pin "2")))
+    (net (code "21") (name "Net-(C6-Pad2)")
+      (node (ref "C6") (pin "2"))
+      (node (ref "R16") (pin "1"))
+      (node (ref "R17") (pin "2")))
+    (net (code "22") (name "Net-(C7-Pad1)")
+      (node (ref "C7") (pin "1"))
+      (node (ref "R17") (pin "1"))
+      (node (ref "U4") (pin "5") (pinfunction "+")))
+    (net (code "23") (name "Net-(C8-Pad1)")
+      (node (ref "C8") (pin "1"))
+      (node (ref "R20") (pin "2")))
+    (net (code "24") (name "Net-(D2-Pad1)")
+      (node (ref "D2") (pin "1") (pinfunction "K"))
+      (node (ref "D3") (pin "2") (pinfunction "A")))
+    (net (code "25") (name "Net-(D3-Pad1)")
+      (node (ref "D3") (pin "1") (pinfunction "K"))
+      (node (ref "Q1") (pin "2") (pinfunction "B"))
+      (node (ref "R4") (pin "1")))
+    (net (code "26") (name "Net-(D4-Pad1)")
+      (node (ref "D4") (pin "1") (pinfunction "K"))
+      (node (ref "Q3") (pin "2") (pinfunction "B"))
+      (node (ref "Q4") (pin "3") (pinfunction "C"))
+      (node (ref "R10") (pin "1")))
+    (net (code "27") (name "Net-(D4-Pad2)")
+      (node (ref "D4") (pin "2") (pinfunction "A"))
+      (node (ref "D8") (pin "1") (pinfunction "K")))
+    (net (code "28") (name "Net-(D5-Pad1)")
+      (node (ref "D5") (pin "1") (pinfunction "K"))
+      (node (ref "D6") (pin "2") (pinfunction "A")))
+    (net (code "29") (name "Net-(D6-Pad1)")
+      (node (ref "D6") (pin "1") (pinfunction "K"))
+      (node (ref "Q5") (pin "2") (pinfunction "B"))
+      (node (ref "R14") (pin "1")))
+    (net (code "30") (name "Net-(D7-Pad1)")
+      (node (ref "D7") (pin "1") (pinfunction "K"))
+      (node (ref "Q7") (pin "2") (pinfunction "B"))
+      (node (ref "Q8") (pin "3") (pinfunction "C"))
+      (node (ref "R20") (pin "1")))
+    (net (code "31") (name "Net-(D7-Pad2)")
+      (node (ref "D7") (pin "2") (pinfunction "A"))
+      (node (ref "D9") (pin "1") (pinfunction "K")))
+    (net (code "32") (name "Net-(D8-Pad2)")
+      (node (ref "D8") (pin "2") (pinfunction "A"))
+      (node (ref "Q1") (pin "3") (pinfunction "C"))
+      (node (ref "Q2") (pin "2") (pinfunction "B")))
+    (net (code "33") (name "Net-(D9-Pad2)")
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+      (node (ref "Q1") (pin "1") (pinfunction "E"))
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+      (node (ref "R5") (pin "2")))
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+      (node (ref "R13") (pin "2")))
+    (net (code "40") (name "Net-(Q6-Pad1)")
+      (node (ref "Q6") (pin "1") (pinfunction "E"))
+      (node (ref "R15") (pin "2"))
+      (node (ref "R28") (pin "2")))
+    (net (code "41") (name "Net-(Q7-Pad1)")
+      (node (ref "Q7") (pin "1") (pinfunction "E"))
+      (node (ref "R22") (pin "2"))
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+    (net (code "42") (name "Net-(Q8-Pad1)")
+      (node (ref "Q8") (pin "1") (pinfunction "E"))
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+    (net (code "43") (name "Net-(Q8-Pad2)")
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+    (net (code "44") (name "Net-(R11-Pad1)")
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+    (net (code "45") (name "Net-(R19-Pad2)")
+      (node (ref "R19") (pin "2"))
+      (node (ref "U4") (pin "1")))
+    (net (code "46") (name "Net-(R21-Pad1)")
+      (node (ref "R21") (pin "1"))
+      (node (ref "RV2") (pin "1") (pinfunction "1")))
+    (net (code "47") (name "Net-(R9-Pad2)")
+      (node (ref "R9") (pin "2"))
+      (node (ref "U3") (pin "1")))
+    (net (code "48") (name "Net-(RV1-Pad2)")
+      (node (ref "RV1") (pin "2") (pinfunction "2"))
+      (node (ref "U3") (pin "2") (pinfunction "-")))
+    (net (code "49") (name "Net-(RV2-Pad2)")
+      (node (ref "RV2") (pin "2") (pinfunction "2"))
+      (node (ref "U4") (pin "2") (pinfunction "-")))
+    (net (code "50") (name "Net-(U1-Pad6)")
+      (node (ref "U1") (pin "6") (pinfunction "LV")))
+    (net (code "51") (name "Net-(U1-Pad7)")
+      (node (ref "U1") (pin "7") (pinfunction "OSC")))
+    (net (code "52") (name "VCC")
+      (node (ref "C1") (pin "1"))
+      (node (ref "U1") (pin "8") (pinfunction "V+"))
+      (node (ref "U2") (pin "1") (pinfunction "VO")))))
--- a/qa/eeschema/data/netlists/complex_hierarchy/complex_hierarchy.pro
+++ b/qa/eeschema/data/netlists/complex_hierarchy/complex_hierarchy.pro
@ -0,0 +1,272 @@
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--- a/qa/eeschema/data/netlists/complex_hierarchy/complex_hierarchy.sch
+++ b/qa/eeschema/data/netlists/complex_hierarchy/complex_hierarchy.sch
@ -0,0 +1,445 @@
+EESchema Schematic File Version 5
+EELAYER 30 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 3
+Title "Complex hierarchy: demo"
+Date "2017-01-15"
+Rev ""
+Comp ""
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+P 2200 1650
+F 0 "#U015" H 2200 1920 30  0001 C CNN
+F 1 "PWR_FLAG" H 2200 1880 30  0000 C CNN
+F 2 "" H 2200 1650 10  0001 C CNN
+F 3 "" H 2200 1650 60  0001 C CNN
+	1    2200 1650
+	1    0    0    -1  
+$EndComp
+$Comp
+L complex_hierarchy_schlib:+12V #U016
+U 1 1 4AE173EF
+P 3550 2450
+F 0 "#U016" H 3550 2400 20  0001 C CNN
+F 1 "+12V" H 3550 2550 40  0000 C CNN
+F 2 "" H 3550 2450 10  0001 C CNN
+F 3 "" H 3550 2450 60  0001 C CNN
+	1    3550 2450
+	1    0    0    -1  
+$EndComp
+$Comp
+L complex_hierarchy_schlib:GND #PWR017
+U 1 1 4AE173D0
+P 3200 3000
+F 0 "#PWR017" H 3200 3000 30  0001 C CNN
+F 1 "GND" H 3200 2930 30  0001 C CNN
+F 2 "" H 3200 3000 10  0001 C CNN
+F 3 "" H 3200 3000 60  0001 C CNN
+	1    3200 3000
+	1    0    0    -1  
+$EndComp
+$Comp
+L complex_hierarchy_schlib:CP C2
+U 1 1 4AE173CF
+P 3200 2750
+F 0 "C2" H 3350 2800 50  0000 L CNN
+F 1 "47uF/20V" H 3350 2700 50  0000 L TNN
+F 2 "Capacitor_THT:CP_Axial_L10.0mm_D4.5mm_P15.00mm_Horizontal" H 3550 2600 10  0000 C CNN
+F 3 "" H 3200 2750 60  0001 C CNN
+	1    3200 2750
+	1    0    0    -1  
+$EndComp
+$Comp
+L complex_hierarchy_schlib:D_Small D1
+U 1 1 4AE172F4
+P 2700 2500
+F 0 "D1" H 2700 2400 40  0000 C CNN
+F 1 "1N4007" H 2700 2600 40  0000 C CNN
+F 2 "Diode_THT:D_DO-41_SOD81_P12.70mm_Horizontal" H 2700 2350 10  0000 C CNN
+F 3 "" H 2700 2500 60  0001 C CNN
+	1    2700 2500
+	-1   0    0    -1  
+$EndComp
+$Comp
+L complex_hierarchy_schlib:GND #PWR018
+U 1 1 4AD71B8E
+P 2100 2800
+F 0 "#PWR018" H 2100 2800 30  0001 C CNN
+F 1 "GND" H 2100 2730 30  0001 C CNN
+F 2 "" H 2100 2800 10  0001 C CNN
+F 3 "" H 2100 2800 60  0001 C CNN
+	1    2100 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L complex_hierarchy_schlib:CONN_2 P2
+U 1 1 4AD71B06
+P 1650 2600
+F 0 "P2" V 1600 2600 40  0000 C CNN
+F 1 "CONN_2" V 1700 2600 40  0000 C CNN
+F 2 "TerminalBlock_Altech:Altech_AK300_1x02_P5.00mm_45-Degree" H 1650 2400 10  0000 C CNN
+F 3 "" H 1650 2600 60  0001 C CNN
+	1    1650 2600
+	-1   0    0    -1  
+$EndComp
+Wire Wire Line
+	2200 1250 2200 1300
+Connection ~ 2200 1300
+Wire Wire Line
+	2000 1300 2200 1300
+Wire Wire Line
+	2000 1500 2100 1500
+Wire Wire Line
+	2100 1500 2100 1700
+Wire Wire Line
+	2100 1700 2200 1700
+Connection ~ 2200 1700
+Wire Wire Line
+	9050 2300 9050 2250
+Wire Wire Line
+	9050 2250 9200 2250
+Wire Wire Line
+	7900 2200 7900 2250
+Wire Wire Line
+	7900 1650 7900 1600
+Wire Wire Line
+	7900 3600 7900 3550
+Wire Wire Line
+	9200 2750 9350 2750
+Wire Wire Line
+	2500 1300 2500 1350
+Wire Wire Line
+	3200 2500 3550 2500
+Wire Wire Line
+	3550 2500 3800 2500
+Wire Wire Line
+	3000 2500 3200 2500
+Wire Wire Line
+	9200 1300 9200 1450
+Wire Wire Line
+	2200 1300 2500 1300
+Wire Wire Line
+	2200 1700 2200 1750
+$EndSCHEMATC
--- a/qa/eeschema/data/netlists/complex_hierarchy/complex_hierarchy_schlib.lib
+++ b/qa/eeschema/data/netlists/complex_hierarchy/complex_hierarchy_schlib.lib
@ -0,0 +1,324 @@
+EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# +12C
+#
+DEF +12C #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "+12C" 0 150 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 2 0 1 0 -30 50 0 100 N
+P 2 0 1 0 0 0 0 100 N
+P 2 0 1 0 0 100 30 50 N
+X +12C 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# +12V
+#
+DEF +12V #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "+12V" 0 140 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 2 0 1 0 -30 50 0 100 N
+P 2 0 1 0 0 0 0 100 N
+P 2 0 1 0 0 100 30 50 N
+X +12V 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# -VAA
+#
+DEF -VAA #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 100 20 H I C CNN
+F1 "-VAA" 0 100 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 3 0 1 0 0 0 0 50 0 50 N
+P 7 0 1 0 0 80 30 50 -20 50 -30 50 0 80 0 80 0 80 F
+X -VAA 1 0 0 0 U 20 20 0 0 W N
+ENDDRAW
+ENDDEF
+#
+# 7805
+#
+DEF 7805 U 0 20 Y Y 1 F N
+F0 "U" 150 -196 60 H V C CNN
+F1 "7805" 0 200 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS 78L05 LM7805 LM7812
+DRAW
+S -200 -150 200 150 0 1 0 N
+X VO 1 400 50 200 L 30 40 1 1 w
+X GND 2 0 -250 100 U 30 40 1 1 I
+X VI 3 -400 50 200 R 30 40 1 1 I
+ENDDRAW
+ENDDEF
+#
+# C
+#
+DEF C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ C?
+ C_????_*
+ C_????
+ SMD*_c
+ Capacitor*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# CONN_2
+#
+DEF CONN_2 P 0 40 Y N 1 F N
+F0 "P" -50 0 40 V V C CNN
+F1 "CONN_2" 50 0 40 V V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -100 150 100 -150 0 1 0 N
+X P1 1 -350 100 250 R 60 60 1 1 P I
+X PM 2 -350 -100 250 R 60 60 1 1 P I
+ENDDRAW
+ENDDEF
+#
+# CP
+#
+DEF CP C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "CP" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ CP*
+ Elko*
+ TantalC*
+ C*elec
+ c_elec*
+ SMD*_Pol
+$ENDFPLIST
+DRAW
+S -90 20 -90 40 0 1 0 N
+S -90 20 90 20 0 1 0 N
+S -70 90 -30 90 0 1 0 N
+S -50 70 -50 110 0 1 0 N
+S 90 -20 -90 -40 0 1 0 F
+S 90 40 -90 40 0 1 0 N
+S 90 40 90 20 0 1 0 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# D_Small
+#
+DEF D_Small D 0 10 N N 1 F N
+F0 "D" -50 80 50 H V L CNN
+F1 "D_Small" -150 -80 50 H V L CNN
+F2 "" 0 0 60 V V C CNN
+F3 "" 0 0 60 V V C CNN
+$FPLIST
+ Diode_*
+ D-Pak_TO252AA
+ *SingleDiode
+ *SingleDiode*
+ *_Diode_*
+$ENDFPLIST
+DRAW
+P 2 0 1 0 -30 -40 -30 40 N
+P 4 0 1 0 30 -40 -30 0 30 40 30 -40 F
+X K 1 -100 0 70 R 50 50 1 1 P
+X A 2 100 0 70 L 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "GND" 0 -123 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 20 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# HT
+#
+DEF HT #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 120 50 H I C CNN
+F1 "HT" 0 90 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 3 0 1 0 0 0 0 40 0 40 N
+P 6 0 1 0 0 40 20 20 0 70 -20 20 0 40 0 40 N
+X HT 1 0 0 0 U 20 20 0 0 W N
+ENDDRAW
+ENDDEF
+#
+# ICL7660
+#
+DEF ICL7660 U 0 40 Y Y 1 F N
+F0 "U" 200 400 70 H V L CNN
+F1 "ICL7660" 50 -450 70 H V L CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -550 -350 550 350 0 1 0 N
+X CAP+ 2 -850 250 300 R 60 60 1 1 I
+X GND 3 -50 -650 300 U 60 60 1 1 W
+X CAP- 4 -850 50 300 R 60 60 1 1 I
+X VOUT 5 850 150 300 L 60 60 1 1 w
+X LV 6 850 -150 300 L 60 60 1 1 I
+X OSC 7 -850 -150 300 R 60 60 1 1 I
+X V+ 8 -50 650 300 D 60 60 1 1 W
+ENDDRAW
+ENDDEF
+#
+# LM358
+#
+DEF LM358 U 0 20 Y Y 2 F N
+F0 "U" -50 200 60 H V L CNN
+F1 "LM358" -50 -250 60 H V L CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS LM358N LMC6062 LMC6082 TL072 TL082
+DRAW
+P 4 0 1 6 -200 200 200 0 -200 -200 -200 200 f
+X V- 4 -100 -400 250 U 40 40 0 1 W
+X V+ 8 -100 400 250 D 40 40 0 1 W
+X ~ 1 500 0 300 L 40 40 1 1 O
+X - 2 -500 -100 300 R 40 40 1 1 I
+X + 3 -500 100 300 R 40 40 1 1 I
+X + 5 -500 100 300 R 40 40 2 1 I
+X - 6 -500 -100 300 R 40 40 2 1 I
+X ~ 7 500 0 300 L 40 40 2 1 O
+ENDDRAW
+ENDDEF
+#
+# MPSA42
+#
+DEF MPSA42 Q 0 0 Y Y 1 F N
+F0 "Q" 150 -150 60 H V L CNN
+F1 "MPSA42" 150 150 60 H V L CNN
+F2 "TO92-CBE" 150 0 30 H I C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ TO92-CBE
+$ENDFPLIST
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 0 0 100 100 N
+P 3 0 1 10 0 75 0 -75 0 -75 N
+P 3 0 1 0 50 -50 0 0 0 0 N
+P 3 0 1 0 90 -90 100 -100 100 -100 N
+P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F
+X E 1 100 -200 100 U 20 20 1 1 P
+X B 2 -200 0 200 R 20 20 1 1 I
+X C 3 100 200 100 D 20 20 1 1 P
+ENDDRAW
+ENDDEF
+#
+# MPSA92
+#
+DEF MPSA92 Q 0 0 Y Y 1 F N
+F0 "Q" 150 -150 60 H V L CNN
+F1 "MPSA92" 150 150 60 H V L CNN
+F2 "TO92-CBE" 150 0 30 H I C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ TO92-CBE
+$ENDFPLIST
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 0 0 100 100 N
+P 3 0 1 10 0 75 0 -75 0 -75 F
+P 3 0 1 0 25 -25 0 0 0 0 N
+P 3 0 1 0 100 -100 65 -65 65 -65 N
+P 5 0 1 0 25 -25 50 -75 75 -50 25 -25 25 -25 F
+X E 1 100 -200 100 U 20 20 1 1 P
+X B 2 -200 0 200 R 20 20 1 1 I
+X C 3 100 200 100 D 20 20 1 1 P
+ENDDRAW
+ENDDEF
+#
+# POT
+#
+DEF POT RV 0 40 Y N 1 F N
+F0 "RV" 0 -100 50 H V C CNN
+F1 "POT" 0 0 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -150 50 150 -50 0 1 0 N
+P 3 0 1 0 0 50 -20 70 20 70 F
+X 1 1 -250 0 100 R 40 40 1 1 P
+X 2 2 0 150 80 D 40 40 1 1 P
+X 3 3 250 0 100 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 95 50 H I C CNN
+F1 "PWR_FLAG" 0 180 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N
+X pwr 1 0 0 0 U 20 20 0 0 w
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+F2 "" -70 0 30 V V C CNN
+F3 "" 0 0 30 H V C CNN
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S -40 -100 40 100 0 1 10 N
+X ~ 1 0 150 50 D 60 60 1 1 P
+X ~ 2 0 -150 50 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# VCC
+#
+DEF VCC #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "VCC" 0 150 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 75 25 0 1 0 N
+P 2 0 1 0 0 0 0 50 N
+X VCC 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+#End Library
--- a/qa/eeschema/data/netlists/complex_hierarchy/fp-lib-table
+++ b/qa/eeschema/data/netlists/complex_hierarchy/fp-lib-table
@ -0,0 +1,8 @@
+(fp_lib_table
+  (lib (name "Package_DIP")(type "KiCad")(uri "$(KISYSMOD)/Package_DIP.pretty")(options "")(descr ""))
+  (lib (name "Capacitor_THT")(type "KiCad")(uri "$(KISYSMOD)/Capacitor_THT.pretty")(options "")(descr ""))
+  (lib (name "Resistor_THT")(type "KiCad")(uri "$(KISYSMOD)/Resistor_THT.pretty")(options "")(descr ""))
+  (lib (name "Package_TO_SOT_THT")(type "KiCad")(uri "$(KISYSMOD)/Package_TO_SOT_THT.pretty")(options "")(descr ""))
+  (lib (name "TerminalBlock_Altech")(type "KiCad")(uri "${KISYSMOD}/TerminalBlock_Altech.pretty")(options "")(descr ""))
+  (lib (name "Potentiometer_THT")(type "KiCad")(uri "${KISYSMOD}/Potentiometer_THT.pretty")(options "")(descr ""))
+)
--- a/qa/eeschema/data/netlists/complex_hierarchy/sym-lib-table
+++ b/qa/eeschema/data/netlists/complex_hierarchy/sym-lib-table
@ -0,0 +1,3 @@
+(sym_lib_table
+  (lib (name complex_hierarchy_schlib)(type Legacy)(uri ${KIPRJMOD}/complex_hierarchy_schlib.lib)(options "")(descr ""))
+)
--- a/qa/eeschema/data/netlists/test_global_promotion/Sub.sch
+++ b/qa/eeschema/data/netlists/test_global_promotion/Sub.sch
@ -0,0 +1,27 @@
+EESchema Schematic File Version 5
+EELAYER 31 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 2 2
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+Comment5 ""
+Comment6 ""
+Comment7 ""
+Comment8 ""
+Comment9 ""
+$EndDescr
+Wire Wire Line
+	2850 2000 4050 2000
+Text Label 4050 2000 2    50   ~ 0
+5V
+Text GLabel 2850 2000 0    50   Input ~ 0
+5Vanalog
+$EndSCHEMATC
--- a/qa/eeschema/data/netlists/test_global_promotion/test_global_promotion-cache.lib
+++ b/qa/eeschema/data/netlists/test_global_promotion/test_global_promotion-cache.lib
@ -0,0 +1,52 @@
+EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# Device_C
+#
+DEF Device_C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "Device_C" 25 -100 50 H V L CNN
+F2 "" 38 -150 50 H I C CNN
+F3 "~" 0 0 50 H I C CNN
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 50 50 1 1 P
+X ~ 2 0 -150 110 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# Device_R
+#
+DEF Device_R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "Device_R" 0 0 50 V V C CNN
+F2 "" -70 0 50 V I C CNN
+F3 "~" 0 0 50 H I C CNN
+$FPLIST
+ R_*
+$ENDFPLIST
+DRAW
+S -40 -100 40 100 0 1 10 N
+X ~ 1 0 150 50 D 50 50 1 1 P
+X ~ 2 0 -150 50 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# power_GND
+#
+DEF power_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "power_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+#End Library
--- a/qa/eeschema/data/netlists/test_global_promotion/test_global_promotion.net
+++ b/qa/eeschema/data/netlists/test_global_promotion/test_global_promotion.net
@ -0,0 +1,88 @@
+(export (version "D")
+  (design
+    (source "/home/jon/work/kicad-master/qa/eeschema/data/netlists/test_global_promotion/test_global_promotion.sch")
+    (date "Sun 19 Apr 2020 16:13:42 EDT")
+    (tool "Eeschema (5.99.0-1347-g0d2b30b74-dirty)")
+    (sheet (number "1") (name "/") (tstamps "/")
+      (title_block
+        (title)
+        (company)
+        (rev)
+        (date)
+        (source "test_global_promotion.sch")
+        (comment (number "1") (value ""))
+        (comment (number "2") (value ""))
+        (comment (number "3") (value ""))
+        (comment (number "4") (value ""))
+        (comment (number "5") (value ""))
+        (comment (number "6") (value ""))
+        (comment (number "7") (value ""))
+        (comment (number "8") (value ""))
+        (comment (number "9") (value ""))))
+    (sheet (number "2") (name "/Subcircuit/") (tstamps "/00000000-0000-0000-0000-00005e68e19b/")
+      (title_block
+        (title)
+        (company)
+        (rev)
+        (date)
+        (source "Sub.sch")
+        (comment (number "1") (value ""))
+        (comment (number "2") (value ""))
+        (comment (number "3") (value ""))
+        (comment (number "4") (value ""))
+        (comment (number "5") (value ""))
+        (comment (number "6") (value ""))
+        (comment (number "7") (value ""))
+        (comment (number "8") (value ""))
+        (comment (number "9") (value "")))))
+  (components
+    (comp (ref "C1")
+      (value "C")
+      (footprint "Capacitor_THT:CP_Axial_L18.0mm_D8.0mm_P25.00mm_Horizontal")
+      (datasheet "~")
+      (libsource (lib "Device") (part "C") (description "Unpolarized capacitor"))
+      (sheetpath (names "/") (tstamps "/"))
+      (tstamp "00000000-0000-0000-0000-00005e68c688"))
+    (comp (ref "R1")
+      (value "R")
+      (footprint "Resistor_THT:R_Axial_Power_L25.0mm_W6.4mm_P30.48mm")
+      (datasheet "~")
+      (libsource (lib "Device") (part "R") (description "Resistor"))
+      (sheetpath (names "/") (tstamps "/"))
+      (tstamp "00000000-0000-0000-0000-00005e68b6bd")))
+  (libparts
+    (libpart (lib "Device") (part "C")
+      (description "Unpolarized capacitor")
+      (docs "~")
+      (footprints
+        (fp "C_*"))
+      (fields
+        (field (name "Reference") "C")
+        (field (name "Value") "C")
+        (field (name "Datasheet") "~"))
+      (pins
+        (pin (num "1") (name "~") (type "passive"))
+        (pin (num "2") (name "~") (type "passive"))))
+    (libpart (lib "Device") (part "R")
+      (description "Resistor")
+      (docs "~")
+      (footprints
+        (fp "R_*"))
+      (fields
+        (field (name "Reference") "R")
+        (field (name "Value") "R")
+        (field (name "Datasheet") "~"))
+      (pins
+        (pin (num "1") (name "~") (type "passive"))
+        (pin (num "2") (name "~") (type "passive")))))
+  (libraries
+    (library (logical "Device")
+      (uri "/home/jon/kicad-library/kicad-symbols//Device.lib")))
+  (nets
+    (net (code "1") (name "5V")
+      (node (ref "R1") (pin "1")))
+    (net (code "2") (name "5Vanalog")
+      (node (ref "C1") (pin "1"))
+      (node (ref "R1") (pin "2")))
+    (net (code "3") (name "GND")
+      (node (ref "C1") (pin "2")))))
--- a/qa/eeschema/data/netlists/test_global_promotion/test_global_promotion.pro
+++ b/qa/eeschema/data/netlists/test_global_promotion/test_global_promotion.pro
@ -0,0 +1,251 @@
+update=ven. 06 mars 2020 00:05:42 CET
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+[SchematicFrame]
+version=1
+[pcbnew]
+version=1
+PageLayoutDescrFile=
+LastNetListRead=
+LastSTEPExportPath=
+LastIDFExportPath=
+LastVRMLExportPath=
+LastSpecctraDSNExportPath=
+LastGenCADExportPath=
+CopperLayerCount=2
+BoardThickness=1.6
+AllowMicroVias=0
+AllowBlindVias=0
+MinTrackWidth=0.2
+MinViaDiameter=0.4
+MinViaDrill=0.3
+MinMicroViaDiameter=0.2
+MinMicroViaDrill=0.09999999999999999
+MinHoleToHole=0.25
+RequireCourtyardDefinitions=0
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+SolderPasteClearance=0
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+Name=F.Cu
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+Enabled=1
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+Enabled=1
+[pcbnew/Netclasses]
+[pcbnew/Netclasses/Default]
+Name=Default
+Clearance=0.2
+TrackWidth=0.25
+ViaDiameter=0.8
+ViaDrill=0.4
+uViaDiameter=0.3
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+dPairWidth=0.2
+dPairGap=0.25
+dPairViaGap=0.25
+[sheetnames]
+1=00000000-0000-0000-0000-00005e6184cb:Sheet00000000-0000-0000-0000-00005e6184cb
+2=00000000-0000-0000-0000-00005e68e19b:Subcircuit
--- a/qa/eeschema/data/netlists/test_global_promotion/test_global_promotion.sch
+++ b/qa/eeschema/data/netlists/test_global_promotion/test_global_promotion.sch
@ -0,0 +1,75 @@
+EESchema Schematic File Version 5
+EELAYER 31 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 2
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+Comment5 ""
+Comment6 ""
+Comment7 ""
+Comment8 ""
+Comment9 ""
+$EndDescr
+Connection ~ 3650 1700
+Wire Wire Line
+	3000 1700 3250 1700
+Wire Wire Line
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+Wire Wire Line
+	3650 1700 3650 1850
+Wire Wire Line
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+Wire Wire Line
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+$Comp
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+F 3 "" H 3650 2250 50  0001 C CNN
+	1    3650 2250
+	1    0    0    -1  
+$EndComp
+$Comp
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+F 2 "Resistor_THT:R_Axial_Power_L25.0mm_W6.4mm_P30.48mm" V 3330 1700 50  0001 C CNN
+F 3 "~" H 3400 1700 50  0001 C CNN
+	1    3400 1700
+	0    -1   -1   0   
+$EndComp
+$Comp
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+F 2 "Capacitor_THT:CP_Axial_L18.0mm_D8.0mm_P25.00mm_Horizontal" H 3688 1850 50  0001 C CNN
+F 3 "~" H 3650 2000 50  0001 C CNN
+	1    3650 2000
+	1    0    0    -1  
+$EndComp
+$Sheet
+S 4900 1500 450  600 
+U 5E68E19B
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+F1 "Sub.sch" 50
+$EndSheet
+$EndSCHEMATC
--- a/qa/eeschema/data/netlists/video/bus_pci.sch
+++ b/qa/eeschema/data/netlists/video/bus_pci.sch
--- a/qa/eeschema/data/netlists/video/esvideo.sch
+++ b/qa/eeschema/data/netlists/video/esvideo.sch
--- a/qa/eeschema/data/netlists/video/graphic.sch
+++ b/qa/eeschema/data/netlists/video/graphic.sch
--- a/qa/eeschema/data/netlists/video/libs/video_schlib.dcm
+++ b/qa/eeschema/data/netlists/video/libs/video_schlib.dcm
@ -0,0 +1,3 @@
+EESchema-DOCLIB  Version 2.0
+#
+#End Doc Library
--- a/qa/eeschema/data/netlists/video/libs/video_schlib.lib
+++ b/qa/eeschema/data/netlists/video/libs/video_schlib.lib
--- a/qa/eeschema/data/netlists/video/modul.sch
+++ b/qa/eeschema/data/netlists/video/modul.sch
@ -0,0 +1,997 @@
+EESchema Schematic File Version 5
+EELAYER 33 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 6 8
+Title "Video"
+Date "Sun 22 Mar 2015"
+Rev "2.0B"
+Comp "Kicad EDA"
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+Comment5 ""
+Comment6 ""
+Comment7 ""
+Comment8 ""
+Comment9 ""
+$EndDescr
+Connection ~ 2500 1800
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+Wire Wire Line
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--- a/qa/eeschema/data/netlists/video/muxdata.sch
+++ b/qa/eeschema/data/netlists/video/muxdata.sch
@ -0,0 +1,669 @@
+EESchema Schematic File Version 5
+EELAYER 33 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 2 8
+Title "Video"
+Date "Sun 22 Mar 2015"
+Rev "2.0B"
+Comp "Kicad EDA"
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+Comment5 ""
+Comment6 ""
+Comment7 ""
+Comment8 ""
+Comment9 ""
+$EndDescr
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--- a/qa/eeschema/data/netlists/video/pal-ntsc.sch
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+Type=0
+Enabled=0
+[pcbnew/Layer.In26.Cu]
+Name=In26.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In27.Cu]
+Name=In27.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In28.Cu]
+Name=In28.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In29.Cu]
+Name=In29.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In30.Cu]
+Name=In30.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.B.Cu]
+Name=bottom_copper
+Type=0
+Enabled=1
+[pcbnew/Layer.B.Adhes]
+Enabled=1
+[pcbnew/Layer.F.Adhes]
+Enabled=1
+[pcbnew/Layer.B.Paste]
+Enabled=1
+[pcbnew/Layer.F.Paste]
+Enabled=1
+[pcbnew/Layer.B.SilkS]
+Enabled=1
+[pcbnew/Layer.F.SilkS]
+Enabled=1
+[pcbnew/Layer.B.Mask]
+Enabled=1
+[pcbnew/Layer.F.Mask]
+Enabled=1
+[pcbnew/Layer.Dwgs.User]
+Enabled=1
+[pcbnew/Layer.Cmts.User]
+Enabled=1
+[pcbnew/Layer.Eco1.User]
+Enabled=1
+[pcbnew/Layer.Eco2.User]
+Enabled=1
+[pcbnew/Layer.Edge.Cuts]
+Enabled=1
+[pcbnew/Layer.Margin]
+Enabled=1
+[pcbnew/Layer.B.CrtYd]
+Enabled=1
+[pcbnew/Layer.F.CrtYd]
+Enabled=1
+[pcbnew/Layer.B.Fab]
+Enabled=1
+[pcbnew/Layer.F.Fab]
+Enabled=1
+[pcbnew/Layer.Rescue]
+Enabled=0
+[pcbnew/Netclasses]
+[pcbnew/Netclasses/Default]
+Name=Default
+Clearance=0.2
+TrackWidth=0.2
+ViaDiameter=0.889
+ViaDrill=0.4
+uViaDiameter=0.508
+uViaDrill=0.127
+dPairWidth=0.2
+dPairGap=0.25
+dPairViaGap=0.25
+[pcbnew/Netclasses/1]
+Name=pwr
+Clearance=0.2
+TrackWidth=0.23
+ViaDiameter=0.889
+ViaDrill=0.4
+uViaDiameter=0.508
+uViaDrill=0.127
+dPairWidth=0.2
+dPairGap=0.25
+dPairViaGap=0.25
--- a/qa/eeschema/data/netlists/video/video.sch
+++ b/qa/eeschema/data/netlists/video/video.sch
--- a/qa/eeschema/netdiff.py
+++ b/qa/eeschema/netdiff.py
@ -80,6 +80,7 @@ if __name__ == '__main__':
    parser = argparse.ArgumentParser(description='Compare KiCad netlists')
    parser.add_argument('first_netlist')
    parser.add_argument('second_netlist')
+    parser.add_argument('--quiet', action='store_true')

    args = parser.parse_args()

@ -97,12 +98,14 @@ if __name__ == '__main__':
    b = extract_nets(b)

    if a is None:
-        print("Could not read nets from {}".format(fn_a))
-        sys.exit(1)
+        if not args.quiet:
+            print("Could not read nets from {}".format(fn_a))
+        sys.exit(-1)

    if b is None:
-        print("Could not read nets from {}".format(fn_b))
-        sys.exit(1)
+        if not args.quiet:
+            print("Could not read nets from {}".format(fn_b))
+        sys.exit(-1)

    nets_a = unpack(a)
    nets_b = unpack(b)
@ -115,47 +118,51 @@ if __name__ == '__main__':
    both = sa & sb

    if len(only_a) == len(only_b) == 0:
-        print("{} and {} are identical".format(fn_a, fn_b))
+        if not args.quiet:
+            print("{} and {} are identical".format(fn_a, fn_b))
        sys.exit(0)

-    print("A: {}\nB: {}".format(fn_a, fn_b))
+    if not args.quiet:
+        print("A: {}\nB: {}".format(fn_a, fn_b))

-    changed_header = False
+        changed_header = False

-    for net_name in sorted(both):
-        if nets_a[net_name] != nets_b[net_name]:
-            if not changed_header:
-                print("\nChanged nets:\n")
-                changed_header = True
+        for net_name in sorted(both):
+            if nets_a[net_name] != nets_b[net_name]:
+                if not changed_header:
+                    print("\nChanged nets:\n")
+                    changed_header = True

-            print("{}: {} => {}".format(net_name, nets_a[net_name],
-                                        nets_b[net_name]))
+                print("{}: {} => {}".format(net_name, nets_a[net_name],
+                                            nets_b[net_name]))

-    discards_a = set()
-    discards_b = set()
+        discards_a = set()
+        discards_b = set()

-    renamed_header = False
+        renamed_header = False

-    for net_name in sorted(only_a):
-        for candidate in only_b:
-            if nets_a[net_name] == nets_b[candidate]:
-                if not renamed_header:
-                    print("\nRenamed nets (no connection changes):\n")
-                    renamed_header = True
+        for net_name in sorted(only_a):
+            for candidate in only_b:
+                if nets_a[net_name] == nets_b[candidate]:
+                    if not renamed_header:
+                        print("\nRenamed nets (no connection changes):\n")
+                        renamed_header = True

-                print("{} => {}".format(net_name, candidate))
-                discards_a.add(net_name)
-                discards_b.add(candidate)
+                    print("{} => {}".format(net_name, candidate))
+                    discards_a.add(net_name)
+                    discards_b.add(candidate)

-    only_a.difference_update(discards_a)
-    only_b.difference_update(discards_b)
+        only_a.difference_update(discards_a)
+        only_b.difference_update(discards_b)

-    if len(only_a) > 0:
-        print("\nOnly in {}:\n".format(fn_a))
-        print('\n'.join(["{}: {}".format(el, nets_a[el])
-                        for el in sorted(only_a)]))
+        if len(only_a) > 0:
+            print("\nOnly in {}:\n".format(fn_a))
+            print('\n'.join(["{}: {}".format(el, nets_a[el])
+                            for el in sorted(only_a)]))

-    if len(only_b) > 0:
-        print("\nOnly in {}:\n".format(fn_b))
-        print('\n'.join(["{}: {}".format(el, nets_b[el])
-                        for el in sorted(only_b)]))
+        if len(only_b) > 0:
+            print("\nOnly in {}:\n".format(fn_b))
+            print('\n'.join(["{}: {}".format(el, nets_b[el])
+                            for el in sorted(only_b)]))
+
+    sys.exit(1)
--- a/qa/eeschema/test_netlists.py
+++ b/qa/eeschema/test_netlists.py
@ -0,0 +1,85 @@
+#!/usr/bin/env python3
+
+# This program source code file is part of KiCad, a free EDA CAD application.
+#
+# Copyright (C) 2020 Jon Evans <jon@craftyjon.com>
+# Copyright (C) 2020 KiCad Developers, see AUTHORS.txt for contributors.
+#
+# This program is free software: you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the
+# Free Software Foundation, either version 3 of the License, or (at your
+# option) any later version.
+#
+# This program is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+# General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+
+import argparse
+import os
+import subprocess
+import sys
+
+
+if __name__ == '__main__':
+
+    parser = argparse.ArgumentParser(description='Tests eeschema netlist generation')
+    parser.add_argument('--initialize', action='store_true',
+                        help='Generates the "good" reference netlists for each test case')
+    parser.add_argument('binary_dir', default='.')
+
+    args = parser.parse_args()
+
+    eeschema = os.path.abspath(os.path.join(args.binary_dir, 'eeschema/eeschema'))
+
+    print('eeschema binary: {}'.format(eeschema))
+
+    # The way we discover testcases is simple:
+    #
+    # The root directory is hardcoded as ./data/netlists
+    # Inside that are testcases in folders.
+    #
+    # Each testcase must have the root sheet named the same as the folder, for example:
+    #   ./data/netlists/video/video.sch
+    #
+    # The good netlist will be stored as ./data/netlists/video/video.net
+    # The test netlist will be generated as ./data/netlists/video/video_test.net
+
+    data_dir = os.path.join(os.getcwd(), 'data/netlists')
+
+    with os.scandir(data_dir) as it:
+        for entry in it:
+            if entry.is_dir():
+
+                project = entry.name
+                project_dir = os.path.join(data_dir, project)
+
+                sch_file = os.path.join(project_dir, project + '.sch')
+                good_net_file = os.path.join(project_dir, project + '.net')
+
+                net_file = good_net_file if args.initialize else os.path.join(
+                        project_dir, project + '_test.net')
+
+                if not os.path.exists(good_net_file) and not args.initialize:
+                    print("FAILED: {} missing good netlist file for comparison".format(project))
+                    sys.exit(-1)
+
+                subprocess.run([eeschema, '--netlist', net_file, sch_file], cwd=project_dir)
+
+                result = subprocess.run(['./netdiff.py', good_net_file, net_file],
+                                        stdout=subprocess.PIPE)
+
+                if not args.initialize:
+                    os.remove(net_file)
+
+                if result.returncode != 0:
+                    print("FAILED: {} netlist does not match:".format(project))
+                    print(result.stdout)
+
+                    sys.exit(result.returncode)
+
+    sys.exit(0)