From 793411aaeb79e96e009318bbbd5c2babb2ce1ca1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=EA=B9=80=EB=9E=91=EA=B8=B0?= Date: Sun, 3 Mar 2024 06:39:20 +0000 Subject: [PATCH] Translated using Weblate (Korean) Currently translated at 100.0% (9258 of 9258 strings) Translation: KiCad EDA/master source Translate-URL: https://hosted.weblate.org/projects/kicad/master-source/ko/ --- translation/pofiles/ko.po | 488 +++++++++++++++++++++++++++++++++++++- 1 file changed, 482 insertions(+), 6 deletions(-) diff --git a/translation/pofiles/ko.po b/translation/pofiles/ko.po index 566eef13f8..9a95a02858 100644 --- a/translation/pofiles/ko.po +++ b/translation/pofiles/ko.po @@ -30,7 +30,7 @@ msgstr "" "Project-Id-Version: kicad\n" "Report-Msgid-Bugs-To: \n" "POT-Creation-Date: 2024-02-28 09:55-0800\n" -"PO-Revision-Date: 2024-03-02 05:02+0000\n" +"PO-Revision-Date: 2024-03-04 07:01+0000\n" "Last-Translator: 김랑기 \n" "Language-Team: Korean \n" @@ -2771,7 +2771,7 @@ msgstr "USLedger 11x17in" #: common/dialogs/dialog_page_settings.cpp:73 msgid "User (Custom)" -msgstr "사용자 (사용자 정의)" +msgstr "사용자(사용자 정의)" #: common/dialogs/dialog_page_settings.cpp:105 msgid "Preview Settings" @@ -26433,7 +26433,7 @@ msgstr "선형 저항:" #: pcb_calculator/calculator_panels/panel_cable_size_base.cpp:126 #, c-format msgid "Frequency for 100% skin depth:" -msgstr "침투 깊이 100% 를 위한 주파수:" +msgstr "100% 표면 깊이를 위한 주파수:" #: pcb_calculator/calculator_panels/panel_cable_size_base.cpp:138 msgid "Ampacity:" @@ -29686,7 +29686,7 @@ msgstr "N/A" #: pcbnew/dialogs/dialog_board_statistics.cpp:504 pcbnew/pad.cpp:1254 msgid "PTH" -msgstr "PTH" +msgstr "도금 관통 홀" #: pcbnew/dialogs/dialog_board_statistics.cpp:504 pcbnew/pad.cpp:1257 msgid "NPTH" @@ -37144,6 +37144,483 @@ msgid "" "For the full documentation see [https://docs.kicad.org](https://docs.kicad." "org/GetMajorMinorVersion/en/pcbnew/pcbnew.html#custom_design_rules)." msgstr "" +"### Top-level Clauses\n" +"\n" +" (version )\n" +"\n" +" (rule ...)\n" +"\n" +"\n" +"
\n" +"\n" +"### Rule Clauses\n" +"\n" +" (constraint ...)\n" +"\n" +" (condition \"\")\n" +"\n" +" (layer \"\")\n" +"\n" +" (severity )\n" +"\n" +"\n" +"
\n" +"\n" +"### Constraints\n" +"\n" +"| Constraint type | Argument type " +" | Desc" +"ription " +" " +" " +" " +" " +" |\n" +"|---------------------------|------------------------------------------------" +"-----------------------------------------------------------------------|-----" +"-----------------------------------------------------------------------------" +"-----------------------------------------------------------------------------" +"-----------------------------------------------------------------------------" +"-----------------------------------------------------------------------------" +"-----------------------------------------------------------------------------" +"--------------------------------------------------|\n" +"| `annular_width` | min/opt/max " +" | " +"Checks the width of annular rings on vias.
" +" " +" " +" " +" " +" |\n" +"| `assertion` | \"<expression>\" " +" | " +"Checks the given expression.
" +" " +" " +" " +" " +" |\n" +"| `clearance` | min " +" | " +"Specifies the **electrical** clearance between copper objects of different " +"nets. (See `physical_clearance` if you wish to specify clearance between " +"objects regardless of net.)

To allow copper objects to overlap " +"(collide), create a `clearance` constraint with the `min` value less than " +"zero (for example, `-1`).
" +" |\n" +"| `courtyard_clearance` | min " +" | " +"Checks the clearance between footprint courtyards and generates an error if " +"any two courtyards are closer than the `min` distance. If a footprint does " +"not have a courtyard shape, no errors will be generated from this constraint." +"
" +" " +" |\n" +"| `diff_pair_gap` | min/opt/max " +" | " +"Checks the gap between coupled tracks in a differential pair. Coupled " +"tracks are segments that are parallel to each other. Differential pair gap " +"is not tested on uncoupled portions of a differential pair (for example, the " +"fanout from a component).
" +" " +" |\n" +"| `diff_pair_uncoupled` | max " +" | " +"Checks the distance that a differential pair track is routed uncoupled from " +"the other polarity track in the pair (for example, where the pair fans out " +"from a component, or becomes uncoupled to pass around another object such as " +"a via).
" +" " +" |\n" +"| `disallow` | `track`
`via`
`micro_via`
`buried_via`" +"
`pad`
`zone`
`text`
`graphic`
`hole`
`footprint`
| " +"Specify one or more object types to disallow, separated by spaces. For " +"example, `(constraint disallow track)` or `(constraint disallow track via " +"pad)`. If an object of this type matches the rule condition, a DRC error " +"will be created.

This constraint is essentially the same as a keepout " +"rule area, but can be used to create more specific keepout restrictions.
" +" |\n" +"| `edge_clearance` | min/opt/max " +" | " +"Checks the clearance between objects and the board edge.

This can " +"also be thought of as the \"milling tolerance\" as the board edge will " +"include all graphical items on the `Edge.Cuts` layer as well as any *oval* " +"pad holes. (See `physical_hole_clearance` for the drilling tolerance.)
" +" " +" |\n" +"| `length` | min/max " +" | " +"Checks the total routed length for the nets that match the rule condition " +"and generates an error for each net that is below the `min` value (if " +"specified) or above the `max` value (if specified) of the constraint.
" +" " +" " +" |\n" +"| `hole` | min/max " +" | " +"Checks the size (diameter) of a drilled hole in a pad or via. For oval " +"holes, the smaller (minor) diameter will be tested against the `min` value (" +"if specified) and the larger (major) diameter will be tested against the " +"`max` value (if specified).
" +" " +" |\n" +"| `hole_clearance` | min " +" | " +"Checks the clearance between a drilled hole in a pad or via and copper " +"objects on a different net. The clearance is measured from the diameter of " +"the hole, not its center.
" +" " +" " +" |\n" +"| `hole_to_hole` | min " +" | " +"Checks the clearance between mechanically-drilled holes in pads and vias. " +"The clearance is measured between the diameters of the holes, not between " +"their centers.

This constraint is soley for the protection of drill " +"bits. The clearance between **laser-drilled** (microvias) and other non-" +"mechanically-drilled holes is not checked, nor is the clearance between " +"**milled** (oval-shaped) and other non-mechanically-drilled holes.
|\n" +"| `physical_clearance` | min " +" | " +"Checks the clearance between two objects on a given layer (including non-" +"copper layers).

While this can perform more general-purpose checks " +"than `clearance`, it is much slower. Use `clearance` where possible.
" +" " +" " +" |\n" +"| `physical_hole_clearance` | min " +" | " +"Checks the clearance between a drilled hole in a pad or via and another " +"object, regardless of net. The clearance is measured from the diameter of " +"the hole, not its center.

This can also be thought of as the " +"\"drilling tolerance\" as it only includes **round** holes (see " +"`edge_clearance` for the milling tolerance).
" +" " +" |\n" +"| `silk_clearance` | min/opt/max " +" | " +"Checks the clearance between objects on silkscreen layers and other objects.<" +"br> " +" " +" " +" " +" |\n" +"| `skew` | max " +" | " +"Checks the total skew for the nets that match the rule condition, that is, " +"the difference between the length of each net and the average of all the " +"lengths of each net that is matched by the rule. If the absolute value of " +"the difference between that average and the length of any one net is above " +"the constraint `max` value, an error will be generated.
" +" |\n" +"| `thermal_relief_gap` | min " +" | " +"Specifies the width of the gap between a pad and a zone with a thermal-" +"relief connection.
" +" " +" " +" " +" |\n" +"| `thermal_spoke_width` | opt " +" | " +"Specifies the width of the spokes connecting a pad to a zone with a thermal-" +"relief connection.
" +" " +" " +" " +" |\n" +"| `track_width` | min/opt/max " +" | " +"Checks the width of track and arc segments. An error will be generated for " +"each segment that has a width below the `min` value (if specified) or above " +"the `max` value (if specified).
" +" " +" " +" |\n" +"| `via_count` | max " +" | " +"Counts the number of vias on every net matched by the rule condition. If " +"that number exceeds the constraint `max` value on any matched net, an error " +"will be generated for that net.
" +" " +" " +" |\n" +"| `zone_connection` | `solid`
`thermal_reliefs`
`none` " +" | " +"Specifies the connection to be made between a zone and a pad.
" +" " +" " +" " +" " +" |\n" +"\n" +"\n" +"### Items\n" +"\n" +" * `A`    _the first (or only) item under test_\n" +" * `B`    _the second item under test (for binary tests)_\n" +" * `L`    _the layer currently under test_\n" +"\n" +"
\n" +"\n" +"### Severity Names\n" +"\n" +" * warning\n" +" * error\n" +" * exclusion\n" +" * ignore\n" +"\n" +"
\n" +"\n" +"### Examples\n" +"\n" +" (version 1)\n" +"\n" +" (rule HV\n" +" (constraint clearance (min 1.5mm))\n" +" (condition \"A.NetClass == 'HV'\"))\n" +"\n" +"\n" +" (rule HV\n" +" (layer outer)\n" +" (constraint clearance (min 1.5mm))\n" +" (condition \"A.NetClass == 'HV'\"))\n" +"\n" +"\n" +" (rule HV_HV\n" +" # wider clearance between HV tracks\n" +" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" +" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" +"\n" +"\n" +" (rule HV_unshielded\n" +" (constraint clearance (min 2mm))\n" +" (condition \"A.NetClass == 'HV' && !A.enclosedByArea('Shield*')\"))\n" +"\n" +"\n" +" (rule heavy_thermals\n" +" (constraint thermal_spoke_width (min 0.5mm))\n" +" (condition \"A.NetClass == 'HV'\"))\n" +"

\n" +"\n" +"### Notes\n" +"\n" +"Version clause must be the first clause. It indicates the syntax version of " +"the file so that \n" +"future rules parsers can perform automatic updates. It should be\n" +"set to \"1\".\n" +"\n" +"Rules should be ordered by specificity. Later rules take\n" +"precedence over earlier rules; once a matching rule is found\n" +"no further rules will be checked.\n" +"\n" +"Use Ctrl+/ to comment or uncomment line(s).\n" +"


\n" +"\n" +"### Expression functions\n" +"\n" +"All function parameters support simple wildcards (`*` and `?`).\n" +"

\n" +"\n" +" A.intersectsCourtyard('')\n" +"True if any part of `A` lies within the given footprint's principal " +"courtyard.\n" +"

\n" +"\n" +" A.intersectsFrontCourtyard('')\n" +"True if any part of `A` lies within the given footprint's front courtyard.\n" +"

\n" +"\n" +" A.intersectsBackCourtyard('')\n" +"True if any part of `A` lies within the given footprint's back courtyard.\n" +"

\n" +"\n" +" A.intersectsArea('')\n" +"True if any part of `A` lies within the given zone's outline.\n" +"

\n" +"\n" +" A.enclosedByArea('')\n" +"True if all of `A` lies within the given zone's outline.\n" +"\n" +"NB: this is potentially a more expensive call than `intersectsArea()`. Use " +"`intersectsArea()`\n" +"where possible.\n" +"

\n" +"\n" +" A.getField('')\n" +"The value of the given field. Only footprints have fields, so a field is " +"only returned if\n" +"`A` is a footprint.\n" +"

\n" +"\n" +" A.isPlated()\n" +"True if `A` has a hole which is plated.\n" +"

\n" +"\n" +" A.inDiffPair('')\n" +"True if `A` has a net that is part of the specified differential pair.\n" +"`` is the base name of the differential pair. For example, " +"`inDiffPair('/CLK')`\n" +"matches items in the `/CLK_P` and `/CLK_N` nets.\n" +"

\n" +"\n" +" AB.isCoupledDiffPair()\n" +"True if `A` and `B` are members of the same diff pair.\n" +"

\n" +"\n" +" A.memberOfGroup('')\n" +"True if `A` is a member of the given group. The name can contain wildcards.\n" +"Includes nested membership.\n" +"

\n" +"\n" +" A.memberOfFootprint('|')\n" +"True if `A` is a member of a footprint matching the given reference " +"designator or footprint\n" +"ID. The parameter can contain wildcards.\n" +"\n" +"NB: If matching against a footprint ID is desired, the parameter must " +"contain a ':'.\n" +"

\n" +"\n" +" A.memberOfSheet('')\n" +"True if `A` is a member of the given schematic sheet. The sheet path can " +"contain wildcards.\n" +"

\n" +"\n" +" A.existsOnLayer('')\n" +"True if `A` exists on the given layer. The layer name can be\n" +"either the name assigned in Board Setup > Board Editor Layers or\n" +"the canonical name (ie: `F.Cu`).\n" +"\n" +"NB: this returns true if `A` is on the given layer, independently\n" +"of whether or not the rule is being evaluated for that layer.\n" +"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" +"

\n" +"\n" +"### More Examples\n" +"\n" +" (rule \"copper keepout\"\n" +" (constraint disallow track via zone)\n" +" (condition \"A.intersectsArea('zone3')\"))\n" +"\n" +"\n" +" (rule \"BGA neckdown\"\n" +" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" +" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" +" (condition \"A.intersectsCourtyard('U3')\"))\n" +"\n" +"\n" +" # prevent silk over tented vias\n" +" (rule silk_over_via\n" +" (constraint silk_clearance (min 0.2mm))\n" +" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" +"\n" +"\n" +" (rule \"Distance between Vias of Different Nets\"\n" +" (constraint hole_to_hole (min 0.254mm))\n" +" (condition \"A.Type == 'Via' && B.Type == 'Via' && A.Net != B.Net\"))" +"\n" +"\n" +" (rule \"Clearance between Pads of Different Nets\"\n" +" (constraint clearance (min 3.0mm))\n" +" (condition \"A.Type == 'Pad' && B.Type == 'Pad' && A.Net != B.Net\"))" +"\n" +"\n" +"\n" +" (rule \"Via Hole to Track Clearance\"\n" +" (constraint hole_clearance (min 0.254mm))\n" +" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" +"\n" +" (rule \"Pad to Track Clearance\"\n" +" (constraint clearance (min 0.2mm))\n" +" (condition \"A.Type == 'Pad' && B.Type == 'Track'\"))\n" +"\n" +"\n" +" (rule \"clearance-to-1mm-cutout\"\n" +" (constraint edge_clearance (min 0.8mm))\n" +" (condition \"A.Layer == 'Edge.Cuts' && A.Line_Width == 1.0mm\"))\n" +"\n" +"\n" +" (rule \"Max Drill Hole Size Mechanical\"\n" +" (constraint hole_size (max 6.3mm))\n" +" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" +"\n" +" (rule \"Max Drill Hole Size PTH\"\n" +" (constraint hole_size (max 6.35mm))\n" +" (condition \"A.Pad_Type == 'Through-hole'\"))\n" +"\n" +"\n" +" # Specify an optimal gap for a particular diff-pair\n" +" (rule \"dp clock gap\"\n" +" (constraint diff_pair_gap (opt \"0.8mm\"))\n" +" (condition \"A.inDiffPair('/CLK')\"))\n" +"\n" +" # Specify a larger clearance around any diff-pair\n" +" (rule \"dp clearance\"\n" +" (constraint clearance (min \"1.5mm\"))\n" +" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" +"\n" +"\n" +" # Don't use thermal reliefs on heatsink pads\n" +" (rule heat_sink_pad\n" +" (constraint zone_connection solid)\n" +" (condition \"A.Fabrication_Property == 'Heatsink pad'\"))\n" +"\n" +" # Require all four thermal relief spokes to connect to parent zone\n" +" (rule fully_spoked_pads\n" +" (constraint min_resolved_spokes 4))\n" +"\n" +" # Set thermal relief gap & spoke width for all zones\n" +" (rule defined_relief\n" +" (constraint thermal_relief_gap (min 10mil))\n" +" (constraint thermal_spoke_width (min 12mil)))\n" +"\n" +" # Override thermal relief gap & spoke width for GND and PWR zones\n" +" (rule defined_relief_pwr\n" +" (constraint thermal_relief_gap (min 10mil))\n" +" (constraint thermal_spoke_width (min 12mil))\n" +" (condition \"A.Name == 'zone_GND' || A.Name == 'zone_PWR'\"))\n" +"\n" +"\n" +" # Prevent solder wicking from SMD pads\n" +" (rule holes_in_pads\n" +" (constraint physical_hole_clearance (min 0.2mm))\n" +" (condition \"B.Pad_Type == 'SMD'\"))\n" +"\n" +" # Disallow solder mask margin overrides\n" +" (rule \"disallow solder mask margin overrides\"\n" +" (constraint assertion \"A.Soldermask_Margin_Override == 0mm\")\n" +" (condition \"A.Type == 'Pad'\"))\n" +"\n" +"\n" +" # Enforce a mechanical clearance between components and board edge\n" +" (rule front_mechanical_board_edge_clearance\n" +" (layer \"F.Courtyard\")\n" +" (constraint physical_clearance (min 3mm))\n" +" (condition \"B.Layer == 'Edge.Cuts'\"))\n" +"\n" +"\n" +" # Check current-carrying capacity\n" +" (rule high-current\n" +" (constraint track_width (min 1.0mm))\n" +" (constraint connection_width (min 0.8mm))\n" +" (condition \"A.NetClass == 'Power'\"))\n" +"\n" +"\n" +" # Separate drill bit and milling cutter size constraints\n" +" (rule \"Plated through-hole size\"\n" +" (constraint hole_size (min 0.2mm) (max 6.35mm))\n" +" (condition \"A.isPlated() && A.Hole_Size_X == A.Hole_Size_Y\"))\n" +"\n" +" (rule \"Plated slot size\"\n" +" (constraint hole_size (min 0.5mm))\n" +" (condition \"A.isPlated() && A.Hole_Size_X != A.Hole_Size_Y\"))\n" +"\n" +"\n" +"### 문서\n" +"\n" +"전체 문서는 다음을 참조하세요. [https://docs.kicad.org](https://docs.kicad." +"org/GetMajorMinorVersion/en/pcbnew/pcbnew.html#custom_design_rules)." #: pcbnew/dialogs/panel_setup_teardrops_base.cpp:19 msgid "Default properties for round shapes:" @@ -43719,9 +44196,8 @@ msgid "Item allowed at current location." msgstr "현재 경로에서 항목이 사용 가능합니다." #: pcbnew/tools/board_inspection_tool.cpp:1515 -#, fuzzy msgid "Select a footprint to diff with its library equivalent." -msgstr "상응하는 라이브러리에서 차이를 둘 풋프린트 선택." +msgstr "선택한 풋프린트를 라이브러리의 풋프린트와 비교합니다." #: pcbnew/tools/board_inspection_tool.cpp:1533 msgid "Select a footprint for a footprint associations report."