drc: be more verbose when skipping LVS due to lack of schematic netlist

5 years ago · 43404d4577
1 changed files with 9 additions and 2 deletions
--- a/pcbnew/drc/drc_test_provider_lvs.cpp
+++ b/pcbnew/drc/drc_test_provider_lvs.cpp
@ -211,8 +211,15 @@ bool DRC_TEST_PROVIDER_LVS::Run()
        if( !reportPhase( _( "Checking PCB to schematic parity..." ) ) )
            return false;

-        if( m_drcEngine->GetSchematicNetlist() )
-            testFootprints( *m_drcEngine->GetSchematicNetlist() );
+        auto netlist = m_drcEngine->GetSchematicNetlist();
+
+        if( !netlist )
+        {
+            reportAux( _("No netlist provided, skipping LVS.") );
+            return false;
+        }
+
+        testFootprints( *netlist );

        reportRuleStatistics();
    }