diff --git a/pcbnew/drc/drc_cache_generator.cpp b/pcbnew/drc/drc_cache_generator.cpp index 4ef61c11ae..18b2a25708 100644 --- a/pcbnew/drc/drc_cache_generator.cpp +++ b/pcbnew/drc/drc_cache_generator.cpp @@ -160,7 +160,10 @@ bool DRC_CACHE_GENERATOR::Run() // before we start. for( FOOTPRINT* footprint : m_board->Footprints() ) + { footprint->BuildCourtyardCaches(); + footprint->BuildNetTieCache(); + } std::vector> returns; diff --git a/pcbnew/drc/drc_engine.cpp b/pcbnew/drc/drc_engine.cpp index 45ecf3ff40..7698397b72 100644 --- a/pcbnew/drc/drc_engine.cpp +++ b/pcbnew/drc/drc_engine.cpp @@ -745,6 +745,39 @@ DRC_CONSTRAINT DRC_ENGINE::EvalRules( DRC_CONSTRAINT_T aConstraintType, const BO constraint.SetParentRule( c->constraint.GetParentRule() ); }; + // Handle Footprint net ties, which will zero out the clearance for footprint objects + if( aConstraintType == CLEARANCE_CONSTRAINT && ( ac || bc ) && !a_is_non_copper && !b_is_non_copper ) + { + const FOOTPRINT* footprints[2] = {a ? a->GetParentFootprint() : nullptr, + b ? b->GetParentFootprint() : nullptr}; + const BOARD_ITEM* child_items[2] = {a, b}; + + // These are the items being compared against, so the order is reversed + const BOARD_CONNECTED_ITEM* alt_items[2] = {bc, ac}; + + for( int ii = 0; ii < 2; ++ii ) + { + // We need both a footprint item and a connected item to check for a net tie + if( !footprints[ii] || !alt_items[ii] ) + continue; + + const std::set& netcodes = footprints[ii]->GetNetTieCache( child_items[ii] ); + + auto it = netcodes.find( alt_items[ii]->GetNetCode() ); + + if( it != netcodes.end() ) + { + REPORT( "" ) + REPORT( wxString::Format( _( "Net tie on %s; clearance: 0." ), + EscapeHTML( footprints[ii]->GetItemDescription( this, true ) ) ) ) + + constraint.SetName( _( "net tie" ) ); + constraint.m_Value.SetMin( 0 ); + return constraint; + } + } + } + // Local overrides take precedence over everything *except* board min clearance if( aConstraintType == CLEARANCE_CONSTRAINT || aConstraintType == HOLE_CLEARANCE_CONSTRAINT ) { diff --git a/pcbnew/footprint.cpp b/pcbnew/footprint.cpp index 87018f7e88..2615097ee2 100644 --- a/pcbnew/footprint.cpp +++ b/pcbnew/footprint.cpp @@ -3013,6 +3013,73 @@ void FOOTPRINT::BuildCourtyardCaches( OUTLINE_ERROR_HANDLER* aErrorHandler ) } +void FOOTPRINT::BuildNetTieCache() +{ + m_netTieCache.clear(); + std::map map = MapPadNumbersToNetTieGroups(); + std::map> layer_shapes; + + std::for_each( m_drawings.begin(), m_drawings.end(), + [&]( BOARD_ITEM* item ) + { + if( item->Type() != PCB_SHAPE_T ) + return; + + for( PCB_LAYER_ID layer : item->GetLayerSet() ) + layer_shapes[layer].push_back( static_cast( item ) ); + } ); + + for( size_t ii = 0; ii < m_pads.size(); ++ii ) + { + PAD* pad = m_pads[ ii ]; + bool has_nettie = false; + + auto it = map.find( pad->GetNumber() ); + + if( it == map.end() || it->second < 0 ) + continue; + + for( size_t jj = ii + 1; jj < m_pads.size(); ++jj ) + { + PAD* other = m_pads[ jj ]; + + auto it2 = map.find( other->GetNumber() ); + + if( it2 == map.end() || it2->second < 0 ) + continue; + + if( it2->second == it->second ) + { + m_netTieCache[pad].insert( pad->GetNetCode() ); + m_netTieCache[pad].insert( other->GetNetCode() ); + m_netTieCache[other].insert( other->GetNetCode() ); + m_netTieCache[other].insert( pad->GetNetCode() ); + has_nettie = true; + } + } + + if( !has_nettie ) + continue; + + for( auto& [ layer, shapes ] : layer_shapes ) + { + auto pad_shape = pad->GetEffectiveShape( layer ); + + for( auto other_shape : shapes ) + { + auto shape = other_shape->GetEffectiveShape( layer ); + + if( pad_shape->Collide( shape.get() ) ) + { + std::set& nettie = m_netTieCache[pad]; + m_netTieCache[other_shape].insert( nettie.begin(), nettie.end() ); + } + } + } + } +} + + std::map FOOTPRINT::MapPadNumbersToNetTieGroups() const { std::map padNumberToGroupIdxMap; diff --git a/pcbnew/footprint.h b/pcbnew/footprint.h index fce84627b0..521a1f3430 100644 --- a/pcbnew/footprint.h +++ b/pcbnew/footprint.h @@ -499,6 +499,26 @@ public: */ void CheckNetTiePadGroups( const std::function& aErrorHandler ); + /** + * Cache the pads that are allowed to connect to each other in the footprint. + */ + void BuildNetTieCache(); + + /** + * Get the set of net codes that are allowed to connect to a footprint item + */ + const std::set& GetNetTieCache( const BOARD_ITEM* aItem ) const + { + static const std::set emptySet; + + auto it = m_netTieCache.find( aItem ); + + if( it == m_netTieCache.end() ) + return emptySet; + + return it->second; + } + /** * Generate pads shapes on layer \a aLayer as polygons and adds these polygons to * \a aBuffer. @@ -1065,6 +1085,9 @@ private: // A pad group is a comma-separated list of pad numbers. std::vector m_netTiePadGroups; + // A list of 1:N footprint item to allowed net numbers + std::map> m_netTieCache; + // Optional overrides ZONE_CONNECTION m_zoneConnection; std::optional m_clearance; diff --git a/qa/data/pcbnew/issue14008.kicad_pcb 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"viewports": [] + }, + "boards": [], + "cvpcb": { + "equivalence_files": [] + }, + "erc": { + "erc_exclusions": [], + "meta": { + "version": 0 + }, + "pin_map": [ + [ + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 2 + ], + [ + 0, + 2, + 0, + 1, + 0, + 0, + 1, + 0, + 2, + 2, + 2, + 2 + ], + [ + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 1, + 0, + 1, + 2 + ], + [ + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 1, + 2, + 1, + 1, + 2 + ], + [ + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 2 + ], + [ + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 2 + ], + [ + 1, + 1, + 1, + 1, + 1, + 0, + 1, + 1, + 1, + 1, + 1, + 2 + ], + [ + 0, + 0, + 0, + 1, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 2 + ], + [ + 0, + 2, + 1, + 2, + 0, + 0, + 1, + 0, + 2, + 2, + 2, + 2 + ], + [ + 0, + 2, + 0, + 1, + 0, + 0, + 1, + 0, + 2, + 0, + 0, + 2 + ], + [ + 0, + 2, + 1, + 1, + 0, + 0, + 1, + 0, + 2, + 0, + 0, + 2 + ], + [ + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2 + ] + ], + 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"unannotated": "error", + "unit_value_mismatch": "error", + "unresolved_variable": "error", + "wire_dangling": "error" + } + }, + "libraries": { + "pinned_footprint_libs": [], + "pinned_symbol_libs": [] + }, + "meta": { + "filename": "issue14008.kicad_pro", + "version": 1 + }, + "net_settings": { + "classes": [ + { + "bus_width": 12, + "clearance": 0.2, + "diff_pair_gap": 0.25, + "diff_pair_via_gap": 0.25, + "diff_pair_width": 0.2, + "line_style": 0, + "microvia_diameter": 0.3, + "microvia_drill": 0.1, + "name": "Default", + "pcb_color": "rgba(0, 0, 0, 0.000)", + "schematic_color": "rgba(0, 0, 0, 0.000)", + "track_width": 0.25, + "via_diameter": 0.8, + "via_drill": 0.4, + "wire_width": 6 + } + ], + "meta": { + "version": 3 + }, + "net_colors": { + "GND": "rgb(27, 155, 78)", + "GNDD": "rgb(142, 255, 83)" + }, + "netclass_assignments": null, + "netclass_patterns": [] + }, + "pcbnew": { + "last_paths": { + "gencad": "", + "idf": "", + "netlist": "", + "plot": "", + "pos_files": "", + "specctra_dsn": "", + "step": "", + "svg": "", + "vrml": "" + }, + "page_layout_descr_file": "" + }, + "schematic": { + "annotate_start_num": 0, + "bom_export_filename": "", + "bom_fmt_presets": [], + "bom_fmt_settings": { + "field_delimiter": ",", + "keep_line_breaks": false, + "keep_tabs": false, + "name": "CSV", + "ref_delimiter": ",", + "ref_range_delimiter": "", + "string_delimiter": "\"" + }, + "bom_presets": [], + "bom_settings": { + "exclude_dnp": false, + "fields_ordered": [ + { + "group_by": false, + "label": "Reference", + "name": "Reference", + "show": true + }, + { + "group_by": true, + "label": "Value", + "name": "Value", + "show": true + }, + { + "group_by": false, + "label": "Datasheet", + "name": "Datasheet", + "show": true + }, + { + "group_by": false, + "label": "Footprint", + "name": "Footprint", + "show": true + }, + { + "group_by": false, + "label": "Qty", + "name": "${QUANTITY}", + "show": true + }, + { + "group_by": true, + "label": "DNP", + "name": "${DNP}", + "show": true + } + ], + "filter_string": "", + "group_symbols": true, + "name": "Grouped By Value", + "sort_asc": true, + "sort_field": "Reference" + }, + "connection_grid_size": 50.0, + "drawing": { + "dashed_lines_dash_length_ratio": 12.0, + "dashed_lines_gap_length_ratio": 3.0, + "default_line_thickness": 6.0, + "default_text_size": 50.0, + "field_names": [], + "intersheets_ref_own_page": false, + "intersheets_ref_prefix": "", + "intersheets_ref_short": false, + "intersheets_ref_show": false, + "intersheets_ref_suffix": "", + "junction_size_choice": 3, + "label_size_ratio": 0.375, + "operating_point_overlay_i_precision": 3, + "operating_point_overlay_i_range": "~A", + "operating_point_overlay_v_precision": 3, + "operating_point_overlay_v_range": "~V", + "overbar_offset_ratio": 1.23, + "pin_symbol_size": 25.0, + "text_offset_ratio": 0.15 + }, + "legacy_lib_dir": "", + "legacy_lib_list": [], + "meta": { + "version": 1 + }, + "net_format_name": "", + "page_layout_descr_file": "", + "plot_directory": "", + "spice_current_sheet_as_root": false, + "spice_external_command": "spice \"%I\"", + "spice_model_current_sheet_as_root": true, + "spice_save_all_currents": false, + "spice_save_all_dissipations": false, + "spice_save_all_voltages": false, + "subpart_first_id": 65, + "subpart_id_separator": 0 + }, + "sheets": [], + "text_variables": {} +} diff --git a/qa/tests/pcbnew/drc/test_drc_regressions.cpp b/qa/tests/pcbnew/drc/test_drc_regressions.cpp index 1144363946..1f9d4b487e 100644 --- a/qa/tests/pcbnew/drc/test_drc_regressions.cpp +++ b/qa/tests/pcbnew/drc/test_drc_regressions.cpp @@ -63,6 +63,7 @@ BOOST_FIXTURE_TEST_CASE( DRCFalsePositiveRegressions, DRC_REGRESSION_TEST_FIXTUR "issue12609", // Arc collison edge case "issue14412", // Solder mask bridge between pads in a net-tie pad group "issue15280", // Very wide spokes mis-counted as being single spoke + "issue14008", // Net-tie clearance error "unconnected-netnames/unconnected-netnames", // Raised false schematic partity error };