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Update demos to use recent footprints.

pull/13/head
jean-pierre charras 7 years ago
parent
a300ae105d
commit
3cb6dc69f0
11 changed files with 7632 additions and 11172 deletions
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  1. 8
      demos/complex_hierarchy/ampli_ht.sch
  2. 108
      demos/complex_hierarchy/complex_hierarchy-cache.lib
  3. 6686
      demos/complex_hierarchy/complex_hierarchy.kicad_pcb
  4. 8
      demos/complex_hierarchy/complex_hierarchy.sch
  5. 10
      demos/complex_hierarchy/fp-lib-table
  6. 4506
      demos/custom_pads_test/custom_pads_test.kicad_pcb
  7. 11
      demos/interf_u/fp-lib-table
  8. 108
      demos/interf_u/interf_u-cache.lib
  9. 4704
      demos/interf_u/interf_u.kicad_pcb
  10. 9
      demos/interf_u/interf_u.sch
  11. 2646
      demos/sonde xilinx/sonde xilinx.kicad_pcb

8
demos/complex_hierarchy/ampli_ht.sch
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@ -1,6 +1,6 @@
EESchema Schematic File Version 4
EESchema Schematic File Version 5
LIBS:complex_hierarchy-cache
EELAYER 26 0
EELAYER 29 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
@ -458,7 +458,7 @@ AR Path="/4B3A13A4/4B3A136C" Ref="P5" Part="1"
AR Path="/4B3A1333/4B3A136C" Ref="P3" Part="1"
F 0 "P5" V 10700 4400 40 0000 C CNN
F 1 "CONN_2" V 10800 4400 40 0000 C CNN
F 2 "TerminalBlock_Phoenix:TerminalBlock_Phoenix_MKDS-1,5-2-5.08_1x02_P5.08mm_Horizontal" H 10750 4200 10 0000 C CNN
F 2 "TerminalBlock_Altech:Altech_AK300_1x02_P5.00mm_45-Degree" H 10750 4200 10 0000 C CNN
F 3 "" H 10750 4400 60 0001 C CNN
1 10750 4400
1 0 0 -1
@ -525,7 +525,7 @@ AR Path="/4B3A13A4/4B3A1367" Ref="P6" Part="1"
AR Path="/4B3A1333/4B3A1367" Ref="P4" Part="1"
F 0 "P6" V 1300 2100 40 0000 C CNN
F 1 "CONN_2" V 1400 2100 40 0000 C CNN
F 2 "TerminalBlock_Phoenix:TerminalBlock_Phoenix_MKDS-1,5-2-5.08_1x02_P5.08mm_Horizontal" H 1300 1900 10 0000 C CNN
F 2 "TerminalBlock_Altech:Altech_AK300_1x02_P5.00mm_45-Degree" H 1300 1900 10 0000 C CNN
F 3 "" H 1350 2100 60 0001 C CNN
1 1350 2100
-1 0 0 -1

108
demos/complex_hierarchy/complex_hierarchy-cache.lib
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@ -1,11 +1,11 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# complex_hierarchy_schlib:+12C
# complex_hierarchy_schlib_+12C
#
DEF complex_hierarchy_schlib:+12C #PWR 0 0 Y Y 1 F P
DEF complex_hierarchy_schlib_+12C #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "complex_hierarchy_schlib:+12C" 0 150 50 H V C CNN
F1 "complex_hierarchy_schlib_+12C" 0 150 50 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
@ -16,11 +16,11 @@ X +12C 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# complex_hierarchy_schlib:+12V
# complex_hierarchy_schlib_+12V
#
DEF complex_hierarchy_schlib:+12V #PWR 0 0 Y Y 1 F P
DEF complex_hierarchy_schlib_+12V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "complex_hierarchy_schlib:+12V" 0 140 50 H V C CNN
F1 "complex_hierarchy_schlib_+12V" 0 140 50 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
@ -31,11 +31,11 @@ X +12V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# complex_hierarchy_schlib:-VAA
# complex_hierarchy_schlib_-VAA
#
DEF complex_hierarchy_schlib:-VAA #PWR 0 0 Y Y 1 F P
DEF complex_hierarchy_schlib_-VAA #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 100 20 H I C CNN
F1 "complex_hierarchy_schlib:-VAA" 0 100 30 H V C CNN
F1 "complex_hierarchy_schlib_-VAA" 0 100 30 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
@ -45,11 +45,11 @@ X -VAA 1 0 0 0 U 20 20 0 0 W N
ENDDRAW
ENDDEF
#
# complex_hierarchy_schlib:7805
# complex_hierarchy_schlib_7805
#
DEF complex_hierarchy_schlib:7805 U 0 30 N Y 1 F N
DEF complex_hierarchy_schlib_7805 U 0 30 N Y 1 F N
F0 "U" 150 -196 60 H V C CNN
F1 "complex_hierarchy_schlib:7805" 0 200 60 H V C CNN
F1 "complex_hierarchy_schlib_7805" 0 200 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
ALIAS LM7805 LM7812 78L05
@ -61,11 +61,11 @@ X VO VO 400 50 200 L 40 40 1 1 w
ENDDRAW
ENDDEF
#
# complex_hierarchy_schlib:C
# complex_hierarchy_schlib_C
#
DEF complex_hierarchy_schlib:C C 0 10 N Y 1 F N
DEF complex_hierarchy_schlib_C C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "complex_hierarchy_schlib:C" 25 -100 50 H V L CNN
F1 "complex_hierarchy_schlib_C" 25 -100 50 H V L CNN
F2 "" 38 -150 30 H V C CNN
F3 "" 0 0 60 H V C CNN
$FPLIST
@ -83,11 +83,11 @@ X ~ 2 0 -150 110 U 40 40 1 1 P
ENDDRAW
ENDDEF
#
# complex_hierarchy_schlib:CONN_2
# complex_hierarchy_schlib_CONN_2
#
DEF complex_hierarchy_schlib:CONN_2 P 0 40 Y N 1 F N
DEF complex_hierarchy_schlib_CONN_2 P 0 40 Y N 1 F N
F0 "P" -50 0 40 V V C CNN
F1 "complex_hierarchy_schlib:CONN_2" 50 0 40 V V C CNN
F1 "complex_hierarchy_schlib_CONN_2" 50 0 40 V V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
@ -97,11 +97,11 @@ X PM 2 -350 -100 250 R 60 60 1 1 P I
ENDDRAW
ENDDEF
#
# complex_hierarchy_schlib:CP
# complex_hierarchy_schlib_CP
#
DEF complex_hierarchy_schlib:CP C 0 10 N Y 1 F N
DEF complex_hierarchy_schlib_CP C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "complex_hierarchy_schlib:CP" 25 -100 50 H V L CNN
F1 "complex_hierarchy_schlib_CP" 25 -100 50 H V L CNN
F2 "" 38 -150 30 H V C CNN
F3 "" 0 0 60 H V C CNN
$FPLIST
@ -125,11 +125,11 @@ X ~ 2 0 -150 110 U 40 40 1 1 P
ENDDRAW
ENDDEF
#
# complex_hierarchy_schlib:D_Small
# complex_hierarchy_schlib_D_Small
#
DEF complex_hierarchy_schlib:D_Small D 0 10 N N 1 F N
DEF complex_hierarchy_schlib_D_Small D 0 10 N N 1 F N
F0 "D" -50 80 50 H V L CNN
F1 "complex_hierarchy_schlib:D_Small" -150 -80 50 H V L CNN
F1 "complex_hierarchy_schlib_D_Small" -150 -80 50 H V L CNN
F2 "" 0 0 60 V V C CNN
F3 "" 0 0 60 V V C CNN
$FPLIST
@ -147,11 +147,11 @@ X A 2 100 0 70 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# complex_hierarchy_schlib:GND
# complex_hierarchy_schlib_GND
#
DEF complex_hierarchy_schlib:GND #PWR 0 0 Y Y 1 F P
DEF complex_hierarchy_schlib_GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "complex_hierarchy_schlib:GND" 0 -123 30 H V C CNN
F1 "complex_hierarchy_schlib_GND" 0 -123 30 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
@ -160,11 +160,11 @@ X GND 1 0 0 0 D 20 30 1 1 W N
ENDDRAW
ENDDEF
#
# complex_hierarchy_schlib:HT
# complex_hierarchy_schlib_HT
#
DEF complex_hierarchy_schlib:HT #PWR 0 0 Y Y 1 F P
DEF complex_hierarchy_schlib_HT #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 120 50 H I C CNN
F1 "complex_hierarchy_schlib:HT" 0 90 50 H V C CNN
F1 "complex_hierarchy_schlib_HT" 0 90 50 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
@ -174,11 +174,11 @@ X HT 1 0 0 0 U 20 20 0 0 W N
ENDDRAW
ENDDEF
#
# complex_hierarchy_schlib:ICL7660
# complex_hierarchy_schlib_ICL7660
#
DEF complex_hierarchy_schlib:ICL7660 U 0 40 Y Y 1 F N
DEF complex_hierarchy_schlib_ICL7660 U 0 40 Y Y 1 F N
F0 "U" 200 400 70 H V L CNN
F1 "complex_hierarchy_schlib:ICL7660" 50 -450 70 H V L CNN
F1 "complex_hierarchy_schlib_ICL7660" 50 -450 70 H V L CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
@ -193,11 +193,11 @@ X V+ 8 -50 650 300 D 60 60 1 1 W
ENDDRAW
ENDDEF
#
# complex_hierarchy_schlib:LM358N
# complex_hierarchy_schlib_LM358N
#
DEF complex_hierarchy_schlib:LM358N U 0 20 Y Y 2 F N
DEF complex_hierarchy_schlib_LM358N U 0 20 Y Y 2 F N
F0 "U" -50 200 60 H V L CNN
F1 "complex_hierarchy_schlib:LM358N" -50 -250 60 H V L CNN
F1 "complex_hierarchy_schlib_LM358N" -50 -250 60 H V L CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
ALIAS LMC6062 LMC6082 LM358N TL072 TL082
@ -214,11 +214,11 @@ X ~ 7 500 0 300 L 40 40 2 1 O
ENDDRAW
ENDDEF
#
# complex_hierarchy_schlib:MPSA42
# complex_hierarchy_schlib_MPSA42
#
DEF complex_hierarchy_schlib:MPSA42 Q 0 40 Y N 1 F N
DEF complex_hierarchy_schlib_MPSA42 Q 0 40 Y N 1 F N
F0 "Q" 150 -150 60 H V L CNN
F1 "complex_hierarchy_schlib:MPSA42" 150 150 60 H V L CNN
F1 "complex_hierarchy_schlib_MPSA42" 150 150 60 H V L CNN
F2 "TO92-CBE" 150 0 30 H I C CNN
F3 "" 0 0 60 H V C CNN
$FPLIST
@ -237,11 +237,11 @@ X E E 100 -200 100 U 40 40 1 1 P
ENDDRAW
ENDDEF
#
# complex_hierarchy_schlib:MPSA92
# complex_hierarchy_schlib_MPSA92
#
DEF complex_hierarchy_schlib:MPSA92 Q 0 40 Y N 1 F N
DEF complex_hierarchy_schlib_MPSA92 Q 0 40 Y N 1 F N
F0 "Q" 150 -150 60 H V L CNN
F1 "complex_hierarchy_schlib:MPSA92" 150 150 60 H V L CNN
F1 "complex_hierarchy_schlib_MPSA92" 150 150 60 H V L CNN
F2 "TO92-CBE" 150 0 30 H I C CNN
F3 "" 0 0 60 H V C CNN
$FPLIST
@ -260,11 +260,11 @@ X E E 100 -200 100 U 40 40 1 1 P
ENDDRAW
ENDDEF
#
# complex_hierarchy_schlib:POT
# complex_hierarchy_schlib_POT
#
DEF complex_hierarchy_schlib:POT RV 0 40 Y N 1 F N
DEF complex_hierarchy_schlib_POT RV 0 40 Y N 1 F N
F0 "RV" 0 -100 50 H V C CNN
F1 "complex_hierarchy_schlib:POT" 0 0 50 H V C CNN
F1 "complex_hierarchy_schlib_POT" 0 0 50 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
@ -276,11 +276,11 @@ X 3 3 250 0 100 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# complex_hierarchy_schlib:PWR_FLAG
# complex_hierarchy_schlib_PWR_FLAG
#
DEF complex_hierarchy_schlib:PWR_FLAG #FLG 0 0 N N 1 F P
DEF complex_hierarchy_schlib_PWR_FLAG #FLG 0 0 N N 1 F P
F0 "#FLG" 0 95 50 H I C CNN
F1 "complex_hierarchy_schlib:PWR_FLAG" 0 180 50 H V C CNN
F1 "complex_hierarchy_schlib_PWR_FLAG" 0 180 50 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
@ -289,11 +289,11 @@ X pwr 1 0 0 0 U 20 20 0 0 w
ENDDRAW
ENDDEF
#
# complex_hierarchy_schlib:R
# complex_hierarchy_schlib_R
#
DEF complex_hierarchy_schlib:R R 0 0 N Y 1 F N
DEF complex_hierarchy_schlib_R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "complex_hierarchy_schlib:R" 0 0 50 V V C CNN
F1 "complex_hierarchy_schlib_R" 0 0 50 V V C CNN
F2 "" -70 0 30 V V C CNN
F3 "" 0 0 30 H V C CNN
$FPLIST
@ -307,11 +307,11 @@ X ~ 2 0 -150 50 U 60 60 1 1 P
ENDDRAW
ENDDEF
#
# complex_hierarchy_schlib:VCC
# complex_hierarchy_schlib_VCC
#
DEF complex_hierarchy_schlib:VCC #PWR 0 0 Y Y 1 F P
DEF complex_hierarchy_schlib_VCC #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "complex_hierarchy_schlib:VCC" 0 150 50 H V C CNN
F1 "complex_hierarchy_schlib_VCC" 0 150 50 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW

6686
demos/complex_hierarchy/complex_hierarchy.kicad_pcb
File diff suppressed because it is too large
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8
demos/complex_hierarchy/complex_hierarchy.sch
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@ -1,6 +1,6 @@
EESchema Schematic File Version 4
EESchema Schematic File Version 5
LIBS:complex_hierarchy-cache
EELAYER 26 0
EELAYER 29 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
@ -230,7 +230,7 @@ U 1 1 4B3A12F4
P 1650 1400
F 0 "P1" V 1600 1400 40 0000 C CNN
F 1 "CONN_2" V 1700 1400 40 0000 C CNN
F 2 "TerminalBlock_Phoenix:TerminalBlock_Phoenix_MKDS-1,5-2-5.08_1x02_P5.08mm_Horizontal" H 1650 1200 30 0000 C CNN
F 2 "TerminalBlock_Altech:Altech_AK300_1x02_P5.00mm_45-Degree" H 1650 1200 30 0000 C CNN
F 3 "" H 1650 1400 60 0001 C CNN
1 1650 1400
-1 0 0 -1
@ -395,7 +395,7 @@ U 1 1 4AD71B06
P 1650 2600
F 0 "P2" V 1600 2600 40 0000 C CNN
F 1 "CONN_2" V 1700 2600 40 0000 C CNN
F 2 "TerminalBlock_Phoenix:TerminalBlock_Phoenix_MKDS-1,5-2-5.08_1x02_P5.08mm_Horizontal" H 1650 2400 30 0000 C CNN
F 2 "TerminalBlock_Altech:Altech_AK300_1x02_P5.00mm_45-Degree" H 1650 2400 30 0000 C CNN
F 3 "" H 1650 2600 60 0001 C CNN
1 1650 2600
-1 0 0 -1

10
demos/complex_hierarchy/fp-lib-table
View File

@ -1,7 +1,7 @@
(fp_lib_table
(lib (name Package_DIP)(type KiCad)(uri "$(KISYSMOD)/Package_DIP.pretty")(options "")(descr ""))
(lib (name Capacitor_THT)(type KiCad)(uri "$(KISYSMOD)/Capacitor_THT.pretty")(options "")(descr ""))
(lib (name Resistor_THT)(type KiCad)(uri "$(KISYSMOD)/Resistor_THT.pretty")(options "")(descr ""))
(lib (name Package_TO_SOT_THT)(type KiCad)(uri "$(KISYSMOD)/Package_TO_SOT_THT.pretty")(options "")(descr ""))
(lib (name TerminalBlock_Phoenix)(type KiCad)(uri "$(KISYSMOD)/TerminalBlock_Phoenix.pretty")(options "")(descr ""))
(lib (name "Package_DIP")(type "KiCad")(uri "$(KISYSMOD)/Package_DIP.pretty")(options "")(descr ""))
(lib (name "Capacitor_THT")(type "KiCad")(uri "$(KISYSMOD)/Capacitor_THT.pretty")(options "")(descr ""))
(lib (name "Resistor_THT")(type "KiCad")(uri "$(KISYSMOD)/Resistor_THT.pretty")(options "")(descr ""))
(lib (name "Package_TO_SOT_THT")(type "KiCad")(uri "$(KISYSMOD)/Package_TO_SOT_THT.pretty")(options "")(descr ""))
(lib (name "TerminalBlock_Altech")(type "KiCad")(uri "${KISYSMOD}/TerminalBlock_Altech.pretty")(options "")(descr ""))
)

4506
demos/custom_pads_test/custom_pads_test.kicad_pcb
File diff suppressed because it is too large
View File

11
demos/interf_u/fp-lib-table
View File

@ -1,7 +1,8 @@
(fp_lib_table
(lib (name Crystal)(type KiCad)(uri "$(KISYSMOD)/Crystal.pretty")(options "")(descr ""))
(lib (name Connector_Dsub)(type KiCad)(uri "$(KISYSMOD)/Connector_Dsub.pretty")(options "")(descr ""))
(lib (name interf_u)(type KiCad)(uri "$(KIPRJMOD)/interf_u.pretty")(options "")(descr ""))
(lib (name Package_DIP)(type KiCad)(uri "$(KISYSMOD)/Package_DIP.pretty")(options "")(descr ""))
(lib (name Capacitor_THT)(type KiCad)(uri "$(KISYSMOD)/Capacitor_THT.pretty")(options "")(descr ""))
(lib (name "Crystal")(type "KiCad")(uri "$(KISYSMOD)/Crystal.pretty")(options "")(descr ""))
(lib (name "Connector_Dsub")(type "KiCad")(uri "$(KISYSMOD)/Connector_Dsub.pretty")(options "")(descr ""))
(lib (name "interf_u")(type "KiCad")(uri "$(KIPRJMOD)/interf_u.pretty")(options "")(descr ""))
(lib (name "Package_DIP")(type "KiCad")(uri "$(KISYSMOD)/Package_DIP.pretty")(options "")(descr ""))
(lib (name "Capacitor_THT")(type "KiCad")(uri "$(KISYSMOD)/Capacitor_THT.pretty")(options "")(descr ""))
(lib (name "Connector_PinHeader_2.54mm")(type "KiCad")(uri "${KISYSMOD}/Connector_PinHeader_2.54mm.pretty")(options "")(descr ""))
)

108
demos/interf_u/interf_u-cache.lib
View File

@ -1,11 +1,11 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# interf_u_schlib:4003APG120
# interf_u_schlib_4003APG120
#
DEF interf_u_schlib:4003APG120 U 0 40 Y Y 1 F N
DEF interf_u_schlib_4003APG120 U 0 40 Y Y 1 F N
F0 "U" 400 2800 70 H V C CNN
F1 "interf_u_schlib:4003APG120" 0 -2850 70 H V C CNN
F1 "interf_u_schlib_4003APG120" 0 -2850 70 H V C CNN
F2 "PGA120" 0 -2950 40 H V C CNN
F3 "" 400 2800 60 H V C CNN
DRAW
@ -130,11 +130,11 @@ X P N9 1100 100 300 L 60 60 1 1 P
ENDDRAW
ENDDEF
#
# interf_u_schlib:628128
# interf_u_schlib_628128
#
DEF interf_u_schlib:628128 U 0 40 Y Y 1 F N
DEF interf_u_schlib_628128 U 0 40 Y Y 1 F N
F0 "U" 50 0 70 H V C CNN
F1 "interf_u_schlib:628128" 300 -1200 70 H V C CNN
F1 "interf_u_schlib_628128" 300 -1200 70 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
@ -173,11 +173,11 @@ X A3 9 -700 750 300 R 60 60 1 1 I
ENDDRAW
ENDDEF
#
# interf_u_schlib:74LS245
# interf_u_schlib_74LS245
#
DEF interf_u_schlib:74LS245 U 0 40 Y Y 1 L N
DEF interf_u_schlib_74LS245 U 0 40 Y Y 1 L N
F0 "U" -300 650 50 H V C CNN
F1 "interf_u_schlib:74LS245" -300 -650 50 H V C CNN
F1 "interf_u_schlib_74LS245" -300 -650 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS 74HC245
@ -211,11 +211,11 @@ X A7 9 -500 -200 200 R 50 50 1 0 T
ENDDRAW
ENDDEF
#
# interf_u_schlib:74LS541
# interf_u_schlib_74LS541
#
DEF interf_u_schlib:74LS541 U 0 40 Y Y 1 L N
DEF interf_u_schlib_74LS541 U 0 40 Y Y 1 L N
F0 "U" -300 650 50 H V C CNN
F1 "interf_u_schlib:74LS541" -300 -650 50 H V C CNN
F1 "interf_u_schlib_74LS541" -300 -650 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS 74HCT541
@ -250,11 +250,11 @@ X A7 9 -500 -200 200 R 50 50 1 0 I
ENDDRAW
ENDDEF
#
# interf_u_schlib:74LS688
# interf_u_schlib_74LS688
#
DEF interf_u_schlib:74LS688 U 0 40 Y Y 1 L N
DEF interf_u_schlib_74LS688 U 0 40 Y Y 1 L N
F0 "U" -300 1050 50 H V C CNN
F1 "interf_u_schlib:74LS688" -300 -1050 50 H V C CNN
F1 "interf_u_schlib_74LS688" -300 -1050 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
@ -285,11 +285,11 @@ X R3 9 -500 -300 200 R 50 50 1 0 I
ENDDRAW
ENDDEF
#
# interf_u_schlib:Bus_ISA_8bit
# interf_u_schlib_Bus_ISA_8bit
#
DEF interf_u_schlib:Bus_ISA_8bit J 0 40 Y Y 1 F N
DEF interf_u_schlib_Bus_ISA_8bit J 0 40 Y Y 1 F N
F0 "J" 0 1675 50 H V C CNN
F1 "interf_u_schlib:Bus_ISA_8bit" 0 -1675 50 H V C CNN
F1 "interf_u_schlib_Bus_ISA_8bit" 0 -1675 50 H V C CNN
F2 "" -100 1575 30 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
@ -359,11 +359,11 @@ X +12V 9 -900 700 300 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# interf_u_schlib:C
# interf_u_schlib_C
#
DEF interf_u_schlib:C C 0 10 N Y 1 F N
DEF interf_u_schlib_C C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "interf_u_schlib:C" 25 -100 50 H V L CNN
F1 "interf_u_schlib_C" 25 -100 50 H V L CNN
F2 "" 38 -150 30 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
@ -377,11 +377,11 @@ X ~ 2 0 -150 110 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# interf_u_schlib:CP
# interf_u_schlib_CP
#
DEF interf_u_schlib:CP C 0 10 N Y 1 F N
DEF interf_u_schlib_CP C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "interf_u_schlib:CP" 25 -100 50 H V L CNN
F1 "interf_u_schlib_CP" 25 -100 50 H V L CNN
F2 "" 38 -150 30 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
@ -400,11 +400,11 @@ X ~ 2 0 -150 110 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# interf_u_schlib:Conn_02x08_Odd_Even
# interf_u_schlib_Conn_02x08_Odd_Even
#
DEF interf_u_schlib:Conn_02x08_Odd_Even J 0 40 Y N 1 F N
DEF interf_u_schlib_Conn_02x08_Odd_Even J 0 40 Y N 1 F N
F0 "J" 0 450 50 H V C CNN
F1 "interf_u_schlib:Conn_02x08_Odd_Even" 0 -450 50 H V C CNN
F1 "interf_u_schlib_Conn_02x08_Odd_Even" 0 -450 50 H V C CNN
F2 "" -50 50 50 H I C CNN
F3 "" -50 50 50 H I C CNN
$FPLIST
@ -452,11 +452,11 @@ X Pin_9 9 -250 -50 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# interf_u_schlib:Crystal
# interf_u_schlib_Crystal
#
DEF interf_u_schlib:Crystal Y 0 40 N N 1 F N
DEF interf_u_schlib_Crystal Y 0 40 N N 1 F N
F0 "Y" 0 150 50 H V C CNN
F1 "interf_u_schlib:Crystal" 0 -150 50 H V C CNN
F1 "interf_u_schlib_Crystal" 0 -150 50 H V C CNN
F2 "" -100 50 30 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
@ -473,11 +473,11 @@ X 2 2 150 0 50 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# interf_u_schlib:DB25_Female
# interf_u_schlib_DB25_Female
#
DEF interf_u_schlib:DB25_Female J 0 40 Y N 1 F N
DEF interf_u_schlib_DB25_Female J 0 40 Y N 1 F N
F0 "J" 0 1350 50 H V C CNN
F1 "interf_u_schlib:DB25_Female" 0 -1375 50 H V C CNN
F1 "interf_u_schlib_DB25_Female" 0 -1375 50 H V C CNN
F2 "" -100 1250 30 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
@ -563,11 +563,11 @@ X 9 9 -300 -400 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# interf_u_schlib:EP600
# interf_u_schlib_EP600
#
DEF interf_u_schlib:EP600 U 0 40 Y Y 1 F N
DEF interf_u_schlib_EP600 U 0 40 Y Y 1 F N
F0 "U" -100 975 50 H V R CNN
F1 "interf_u_schlib:EP600" -100 900 50 H V R CNN
F1 "interf_u_schlib_EP600" -100 900 50 H V R CNN
F2 "" 50 -800 50 H I L CNN
F3 "" 0 50 50 H I C CNN
DRAW
@ -599,11 +599,11 @@ X I/O9 9 -600 -300 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# interf_u_schlib:GND
# interf_u_schlib_GND
#
DEF interf_u_schlib:GND #PWR 0 0 Y Y 1 F P
DEF interf_u_schlib_GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "interf_u_schlib:GND" 0 -150 50 H V C CNN
F1 "interf_u_schlib_GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
@ -612,11 +612,11 @@ X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# interf_u_schlib:LED
# interf_u_schlib_LED
#
DEF interf_u_schlib:LED D 0 40 Y N 1 F N
DEF interf_u_schlib_LED D 0 40 Y N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "interf_u_schlib:LED" 0 -100 50 H V C CNN
F1 "interf_u_schlib_LED" 0 -100 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
@ -633,11 +633,11 @@ X A 2 150 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# interf_u_schlib:PWR_FLAG
# interf_u_schlib_PWR_FLAG
#
DEF interf_u_schlib:PWR_FLAG #FLG 0 0 N N 1 F P
DEF interf_u_schlib_PWR_FLAG #FLG 0 0 N N 1 F P
F0 "#FLG" 0 75 50 H I C CNN
F1 "interf_u_schlib:PWR_FLAG" 0 150 50 H V C CNN
F1 "interf_u_schlib_PWR_FLAG" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
@ -646,11 +646,11 @@ X pwr 1 0 0 0 U 50 50 0 0 w
ENDDRAW
ENDDEF
#
# interf_u_schlib:R
# interf_u_schlib_R
#
DEF interf_u_schlib:R R 0 0 N Y 1 F N
DEF interf_u_schlib_R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "interf_u_schlib:R" 0 0 50 V V C CNN
F1 "interf_u_schlib_R" 0 0 50 V V C CNN
F2 "" -70 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
@ -664,11 +664,11 @@ X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# interf_u_schlib:RR9
# interf_u_schlib_RR9
#
DEF interf_u_schlib:RR9 RR 0 40 Y N 1 F N
DEF interf_u_schlib_RR9 RR 0 40 Y N 1 F N
F0 "RR" 50 600 70 H V C CNN
F1 "interf_u_schlib:RR9" 30 0 70 V V C CNN
F1 "interf_u_schlib_RR9" 30 0 70 V V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
@ -686,11 +686,11 @@ X 9 9 -350 -300 300 R 60 60 1 1 P I
ENDDRAW
ENDDEF
#
# interf_u_schlib:VCC
# interf_u_schlib_VCC
#
DEF interf_u_schlib:VCC #PWR 0 0 Y Y 1 F P
DEF interf_u_schlib_VCC #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "interf_u_schlib:VCC" 0 150 50 H V C CNN
F1 "interf_u_schlib_VCC" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW

4704
demos/interf_u/interf_u.kicad_pcb
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9
demos/interf_u/interf_u.sch
View File

@ -1,6 +1,6 @@
EESchema Schematic File Version 4
EESchema Schematic File Version 5
LIBS:interf_u-cache
EELAYER 26 0
EELAYER 29 0
EELAYER END
$Descr A3 16535 11693
encoding utf-8
@ -16,7 +16,7 @@ Comment4 "Comment 4"
$EndDescr
$Bitmap
Pos 11050 10550
Scale 1,000000
Scale 1.000000
Data
89 50 4E 47 0D 0A 1A 0A 00 00 00 0D 49 48 44 52 00 00 00 E5 00 00 01 0E 08 02 00 00 00 F9 5F 47
B4 00 00 00 03 73 42 49 54 08 08 08 DB E1 4F E0 00 00 20 00 49 44 41 54 78 9C EC BD 77 94 5D 47
@ -2017,7 +2017,7 @@ U 1 1 32568D1E
P 1700 7250
F 0 "JP1" H 1700 7700 70 0000 C CNN
F 1 "CONN_8X2" V 1700 7250 70 0000 C CNN
F 2 "Pin_Headers:Pin_Header_Straight_2x08" H 1700 7800 20 0000 C CNN
F 2 "Connector_PinHeader_2.54mm:PinHeader_2x08_P2.54mm_Vertical" H 1700 7800 20 0000 C CNN
F 3 "" H 1700 7250 60 0001 C CNN
1 1700 7250
1 0 0 1
@ -2989,6 +2989,7 @@ Wire Wire Line
2200 9400 2850 9400
Wire Wire Line
1650 9400 2200 9400
Connection ~ 4750 2050
Wire Bus Line
3750 1650 3750 2350
Wire Bus Line

2646
demos/sonde xilinx/sonde xilinx.kicad_pcb
File diff suppressed because it is too large
View File

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