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dickelbeck 18 years ago
parent
af445e70ea
commit
14cd0109aa
8 changed files with 221 additions and 72 deletions
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  1. 9
      pcbnew/class_board.cpp
  2. 7
      pcbnew/class_board.h
  3. 1
      pcbnew/dsn.cpp
  4. 1
      pcbnew/dsn.h
  5. 16
      pcbnew/specctra.cpp
  6. 87
      pcbnew/specctra.h
  7. 170
      pcbnew/specctra_export.cpp
  8. 2
      pcbnew/tracepcb.cpp

9
pcbnew/class_board.cpp
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@ -944,11 +944,10 @@ void BOARD::Show( int nestLevel, std::ostream& os )
p->Show( nestLevel+2, os );
NestedSpace( nestLevel+1, os ) << "</zones>\n";
NestedSpace( nestLevel+1, os ) << "<zoneedges>\n";
p = m_CurrentLimitZone;
for( ; p; p = p->Next() )
p->Show( nestLevel+2, os );
NestedSpace( nestLevel+1, os ) << "</zoneedges>\n";
NestedSpace( nestLevel+1, os ) << "<zone_container>\n";
for( ZONE_CONTAINERS::iterator i=m_ZoneDescriptorList.begin(); i!=m_ZoneDescriptorList.end(); ++i )
(*i)->Show( nestLevel+2, os );
NestedSpace( nestLevel+1, os ) << "</zone_container>\n";
p = (BOARD_ITEM*) m_Son;
for( ; p; p = p->Next() )

7
pcbnew/class_board.h
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@ -18,8 +18,11 @@ class BOARD : public BOARD_ITEM
friend class WinEDA_PcbFrame;
private:
std::vector<MARKER*> m_markers; ///< MARKERs for clearance problems, owned by pointer
std::vector<ZONE_CONTAINER*> m_ZoneDescriptorList; ///< edge zone descriptors, owned by pointer
typedef std::vector<MARKER*> MARKERS; // @todo: switch to boost:ptr_vector, and change ~BOARD()
MARKERS m_markers; ///< MARKERs for clearance problems, owned by pointer
typedef std::vector<ZONE_CONTAINER*> ZONE_CONTAINERS; // @todo: switch to boost::ptr_vector, and change ~BOARD()
ZONE_CONTAINERS m_ZoneDescriptorList; ///< edge zone descriptors, owned by pointer
public:
WinEDA_BasePcbFrame* m_PcbFrame; // Window de visualisation

1
pcbnew/dsn.cpp
View File

@ -306,6 +306,7 @@ const static KEYWORD tokens[] = {
TOKDEF(plane),
TOKDEF(pn),
TOKDEF(point),
TOKDEF(polyline_path), // used by freerouting.com
TOKDEF(polygon),
TOKDEF(position),
TOKDEF(positive_diagonal),

1
pcbnew/dsn.h
View File

@ -298,6 +298,7 @@ enum DSN_T {
T_plane,
T_pn,
T_point,
T_polyline_path,
T_polygon,
T_position,
T_positive_diagonal,

16
pcbnew/specctra.cpp
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@ -826,6 +826,8 @@ void SPECCTRA_DB::doKEEPOUT( KEEPOUT* growth ) throw( IOError )
doCIRCLE( (CIRCLE*) growth->shape );
break;
case T_polyline_path:
tok = T_path;
case T_path:
case T_polygon:
if( growth->shape )
@ -883,6 +885,8 @@ void SPECCTRA_DB::doWINDOW( WINDOW* growth ) throw( IOError )
doCIRCLE( (CIRCLE*) growth->shape );
break;
case T_polyline_path:
tok = T_path;
case T_path:
case T_polygon:
if( growth->shape )
@ -2002,6 +2006,8 @@ void SPECCTRA_DB::doSHAPE( SHAPE* growth ) throw( IOError )
tok = nextTok();
switch( tok )
{
case T_polyline_path:
tok = T_path;
case T_rect:
case T_circle:
case T_path:
@ -2714,7 +2720,9 @@ void SPECCTRA_DB::doWIRE( WIRE* growth ) throw( IOError )
growth->shape = new CIRCLE( growth );
doCIRCLE( (CIRCLE*) growth->shape );
break;
case T_polyline_path:
tok = T_path;
case T_path:
case T_polygon:
if( growth->shape )
@ -2747,7 +2755,7 @@ void SPECCTRA_DB::doWIRE( WIRE* growth ) throw( IOError )
tok = nextTok();
if( tok!=T_fix && tok!=T_route && tok!=T_normal && tok!=T_protect )
expecting( "fix|route|normal|protect" );
growth->type = tok;
growth->wire_type = tok;
needRIGHT();
break;
@ -2854,7 +2862,7 @@ void SPECCTRA_DB::doWIRE_VIA( WIRE_VIA* growth ) throw( IOError )
tok = nextTok();
if( tok!=T_fix && tok!=T_route && tok!=T_normal && tok!=T_protect )
expecting( "fix|route|normal|protect" );
growth->type = tok;
growth->via_type = tok;
needRIGHT();
break;
@ -3468,7 +3476,7 @@ PCB* SPECCTRA_DB::MakePCB()
pcb->structure->rules = new RULE( pcb->structure, T_rule );
pcb->placement = new PLACEMENT( pcb );
pcb->placement->flip_style = T_mirror_first;
//pcb->placement->flip_style = T_mirror_first;
pcb->library = new LIBRARY( pcb );

87
pcbnew/specctra.h
View File

@ -2227,8 +2227,8 @@ public:
/**
* Function LookupIMAGE
* will add the image only if one exactly like it does not alread exist
* in the image list.
* will add the image only if one exactly like it does not already exist
* in the image container.
* @return IMAGE* - the IMAGE which is registered in the LIBRARY that
* matches the argument, and it will be either the argument or
* a previous image which is a duplicate.
@ -2243,6 +2243,53 @@ public:
}
return &images[ndx];
}
/**
* Function FindVia
* searches this LIBRARY for a via which matches the argument.
* @return int - if found the index into the padstack list, else -1.
*/
int FindVia( PADSTACK* aVia )
{
if( via_start_index > -1 )
{
for( unsigned i=via_start_index; i<padstacks.size(); ++i )
{
if( 0 == PADSTACK::Compare( aVia, &padstacks[i] ) )
return (int) i;
}
}
return -1;
}
/**
* Function AppendPADSTACK
* adds the padstack to the padstack container.
*/
void AppendPADSTACK( PADSTACK* aPadstack )
{
aPadstack->SetParent( this );
padstacks.push_back( aPadstack );
}
/**
* Function LookupVia
* will add the via only if one exactly like it does not already exist
* in the padstack container.
* @return PADSTACK* - the PADSTACK which is registered in the LIBRARY that
* matches the argument, and it will be either the argument or
* a previous padstack which is a duplicate.
*/
PADSTACK* LookupVia( PADSTACK* aVia )
{
int ndx = FindVia( aVia );
if( ndx == -1 )
{
AppendPADSTACK( aVia );
return aVia;
}
return &padstacks[ndx];
}
void FormatContents( OUTPUTFORMATTER* out, int nestLevel ) throw( IOError )
{
@ -2671,7 +2718,7 @@ class WIRE : public ELEM
std::string net_id;
int turret;
DSN_T type;
DSN_T wire_type;
DSN_T attr;
std::string shield;
WINDOWS windows;
@ -2686,7 +2733,7 @@ public:
connect = 0;
turret = -1;
type = T_NONE;
wire_type = T_NONE;
attr = T_NONE;
supply = false;
}
@ -2729,8 +2776,8 @@ public:
if( turret >= 0 )
out->Print( 0, "(turrent %d)", turret );
if( type != T_NONE )
out->Print( 0, "(type %s)", LEXER::GetTokenText( type ) );
if( wire_type != T_NONE )
out->Print( 0, "(type %s)", LEXER::GetTokenText( wire_type ) );
if( attr != T_NONE )
out->Print( 0, "(attr %s)", LEXER::GetTokenText( attr ) );
@ -2774,7 +2821,7 @@ class WIRE_VIA : public ELEM
POINTS vertexes;
std::string net_id;
int via_number;
DSN_T type;
DSN_T via_type;
DSN_T attr;
std::string virtual_pin_name;
STRINGS contact_layers;
@ -2786,7 +2833,7 @@ public:
ELEM( T_via, aParent )
{
via_number = -1;
type = T_NONE;
via_type = T_NONE;
attr = T_NONE;
supply = false;
}
@ -2813,7 +2860,7 @@ public:
perLine += out->Print( 0, "%.6g %.6g", i->x, i->y );
}
if( net_id.size() || via_number!=-1 || type!=T_NONE || attr!=T_NONE || supply)
if( net_id.size() || via_number!=-1 || via_type!=T_NONE || attr!=T_NONE || supply)
out->Print( 0, " " );
if( net_id.size() )
@ -2837,14 +2884,14 @@ public:
perLine += out->Print( 0, "(via_number %d)", via_number );
}
if( type != T_NONE )
if( via_type != T_NONE )
{
if( perLine > RIGHTMARGIN )
{
out->Print( 0, "\n" );
perLine = out->Print( nestLevel+1, "%s", "" );
}
perLine += out->Print( 0, "(type %s)", LEXER::GetTokenText( type ) );
perLine += out->Print( 0, "(type %s)", LEXER::GetTokenText( via_type ) );
}
if( attr != T_NONE )
@ -3579,7 +3626,25 @@ class SPECCTRA_DB : public OUTPUTFORMATTER
* LIBRARY::padstacks list that it matches.
*/
void makePADSTACKs( BOARD* aBoard, TYPE_COLLECTOR& aPads );
/**
* Function makeVia
* makes a round through hole PADSTACK using the given Kicad diameter in deci-mils.
* @param aCopperDiameter The diameter of the copper pad.
* @return PADSTACK* - The padstack, which is on the heap only, user must save
* or delete it.
*/
PADSTACK* makeVia( int aCopperDiameter );
/**
* Function makeVia
* makes any kind of PADSTACK using the given Kicad SEGVIA.
* @param aVia The SEGVIA to build the padstack from.
* @return PADSTACK* - The padstack, which is on the heap only, user must save
* or delete it.
*/
PADSTACK* makeVia( const SEGVIA* aVia );
public:

170
pcbnew/specctra_export.cpp
View File

@ -36,6 +36,8 @@
#include "collectors.h"
#include "wxPcbStruct.h" // Change_Side_Module()
#include "pcbstruct.h" // HISTORY_NUMBER
#include "autorout.h" // NET_CODES_OK
using namespace DSN;
@ -61,6 +63,12 @@ void WinEDA_PcbFrame::ExportToSPECCTRA( wxCommandEvent& event )
if( fullFileName == wxEmptyString )
return;
// prepare the EQUIPOTs
if( !( m_Pcb->m_Status_Pcb & NET_CODES_OK ) )
{
//m_Pcb->m_Status_Pcb &= ~(LISTE_PAD_OK);
recalcule_pad_net_code();
}
SPECCTRA_DB db;
bool ok = true;
@ -316,6 +324,56 @@ IMAGE* SPECCTRA_DB::makeIMAGE( MODULE* aModule )
}
PADSTACK* SPECCTRA_DB::makeVia( const SEGVIA* aVia )
{
char name[48];
PADSTACK* padstack = new PADSTACK( pcb->library );
SHAPE* shape = new SHAPE( padstack );
padstack->Append( shape );
// @todo: handle the aVia->Shape() differently for each type of via: MICROVIA, etc.
CIRCLE* circle = new CIRCLE( shape );
shape->SetShape( circle );
double dsnDiameter = scale( aVia->m_Width );
circle->SetDiameter( dsnDiameter );
circle->SetLayerId( "signal" );
snprintf( name, sizeof(name), "Via_%.6g_mil", dsnDiameter );
name[ sizeof(name)-1 ] = 0;
padstack->SetPadstackId( name );
return padstack;
}
PADSTACK* SPECCTRA_DB::makeVia( int aCopperDiameter )
{
char name[48];
PADSTACK* padstack = new PADSTACK( pcb->library );
SHAPE* shape = new SHAPE( padstack );
padstack->Append( shape );
CIRCLE* circle = new CIRCLE( shape );
shape->SetShape( circle );
double dsnDiameter = scale(aCopperDiameter);
circle->SetDiameter( dsnDiameter );
circle->SetLayerId( "signal" );
snprintf( name, sizeof(name), "Via_%.6g_mil", dsnDiameter );
name[ sizeof(name)-1 ] = 0;
padstack->SetPadstackId( name );
return padstack;
}
void SPECCTRA_DB::makePADSTACKs( BOARD* aBoard, TYPE_COLLECTOR& aPads )
{
char name[80]; // padstack name builder
@ -599,7 +657,7 @@ void SPECCTRA_DB::makePADSTACKs( BOARD* aBoard, TYPE_COLLECTOR& aPads )
int defaultViaSize = aBoard->m_BoardSettings->m_CurrentViaSize;
if( defaultViaSize )
{
PADSTACK* padstack = new PADSTACK( pcb->library );
PADSTACK* padstack = makeVia( defaultViaSize );
pcb->library->AddPadstack( padstack );
// remember this index, it is the default via and also the start of the
@ -607,15 +665,7 @@ void SPECCTRA_DB::makePADSTACKs( BOARD* aBoard, TYPE_COLLECTOR& aPads )
// At this index and later are the vias.
pcb->library->SetViaStartIndex( pcb->library->padstacks.size()-1 );
SHAPE* shape = new SHAPE( padstack );
padstack->Append( shape );
CIRCLE* circle = new CIRCLE( shape );
shape->SetShape( circle );
circle->SetLayerId( "signal" );
circle->SetDiameter( scale(defaultViaSize) );
padstack->SetPadstackId( "Via_Default" );
// padstack->SetPadstackId( "Via_Default" ); I like the padstack_id with the size in it.
}
for( int i=0; i<HISTORY_NUMBER; ++i )
@ -627,21 +677,8 @@ void SPECCTRA_DB::makePADSTACKs( BOARD* aBoard, TYPE_COLLECTOR& aPads )
if( viaSize == defaultViaSize )
continue;
PADSTACK* padstack = new PADSTACK( pcb->library );
PADSTACK* padstack = makeVia( viaSize );
pcb->library->AddPadstack( padstack );
SHAPE* shape = new SHAPE( padstack );
padstack->Append( shape );
CIRCLE* circle = new CIRCLE( shape );
shape->SetShape( circle );
circle->SetLayerId( "signal" );
circle->SetDiameter( scale(viaSize) );
snprintf( name, sizeof(name), "Via_%.6g_mil", scale(viaSize) );
name[ sizeof(name)-1 ] = 0;
padstack->SetPadstackId( name );
}
}
@ -923,9 +960,7 @@ void SPECCTRA_DB::FromBOARD( BOARD* aBoard )
delete image;
}
const std::string& imageId = registered->image_id;
COMPONENT* comp = pcb->placement->LookupCOMPONENT( imageId );
COMPONENT* comp = pcb->placement->LookupCOMPONENT( registered->image_id );
PLACE* place = new PLACE( comp );
comp->places.push_back( place );
@ -934,9 +969,8 @@ void SPECCTRA_DB::FromBOARD( BOARD* aBoard )
place->SetVertex( mapPt( module->m_Pos ) );
place->component_id = CONV_TO_UTF8( module->GetReference() );
/* not supported by freerouting.com yet.
// not supported by freerouting.net yet:
place->part_number = CONV_TO_UTF8( module->GetValue() );
*/
// module is flipped from bottom side, set side to T_back
if( module->flag )
@ -945,23 +979,6 @@ void SPECCTRA_DB::FromBOARD( BOARD* aBoard )
}
//-----<via_descriptor>-------------------------------------------------
{
// Output the vias in the padstack list here, by name
VIA* vias = pcb->structure->via;
PADSTACKS& padstacks = pcb->library->padstacks;
int viaNdx = pcb->library->via_start_index;
if( viaNdx != -1 )
{
for( ; viaNdx < (int)padstacks.size(); ++viaNdx )
{
vias->AppendVia( padstacks[viaNdx].padstack_id.c_str() );
}
}
}
//-----<create the nets>------------------------------------------------
{
NETWORK* network = pcb->network;
@ -1007,7 +1024,7 @@ void SPECCTRA_DB::FromBOARD( BOARD* aBoard )
{
// export all of them for now, later we'll decide what controls we need
// on this.
static KICAD_T scanTRACKs[] = { TYPETRACK, EOT };
static const KICAD_T scanTRACKs[] = { TYPETRACK, EOT };
items.Collect( aBoard, scanTRACKs );
@ -1051,7 +1068,9 @@ void SPECCTRA_DB::FromBOARD( BOARD* aBoard )
WIRE* wire = new WIRE( wiring );
wiring->wires.push_back( wire );
wire->net_id = netname;
wire->net_id = netname;
wire->wire_type = T_protect; // @todo, this should be configurable
int kiLayer = track->GetLayer();
int pcbLayer = kicadLayer2pcb[kiLayer];
@ -1067,10 +1086,63 @@ void SPECCTRA_DB::FromBOARD( BOARD* aBoard )
path->AppendPoint( mapPt( track->m_End ) );
}
}
//-----<export the existing real instantiated vias>---------------------
{
// export all of them for now, later we'll decide what controls we need
// on this.
static const KICAD_T scanVIAs[] = { TYPEVIA, EOT };
// @todo vias here.
items.Collect( aBoard, scanVIAs );
for( int i=0; i<items.GetCount(); ++i )
{
SEGVIA* via = (SEGVIA*) items[i];
wxASSERT( via->Type() == TYPEVIA );
PADSTACK* padstack = makeVia( via );
PADSTACK* registered = pcb->library->LookupVia( padstack );
if( padstack != registered )
{
delete padstack;
}
WIRE_VIA* dsnVia = new WIRE_VIA( pcb->wiring );
pcb->wiring->wire_vias.push_back( dsnVia );
dsnVia->padstack_id = registered->padstack_id;
dsnVia->vertexes.push_back( mapPt( via->GetPosition() ) );
int netcode = via->GetNet();
EQUIPOT* equipot = aBoard->FindNet( netcode );
wxASSERT( equipot );
dsnVia->net_id = CONV_TO_UTF8( equipot->m_Netname );
dsnVia->via_type = T_protect; // @todo, this should be configurable
}
}
//-----<via_descriptor>-------------------------------------------------
{
// Output the vias in the padstack list here, by name. This must
// be done after exporting existing vias as WIRE_VIAs.
VIA* vias = pcb->structure->via;
PADSTACKS& padstacks = pcb->library->padstacks;
int viaNdx = pcb->library->via_start_index;
if( viaNdx != -1 )
{
for( ; viaNdx < (int)padstacks.size(); ++viaNdx )
{
vias->AppendVia( padstacks[viaNdx].padstack_id.c_str() );
}
}
}
//-----<restore MODULEs>------------------------------------------------

2
pcbnew/tracepcb.cpp
View File

@ -177,7 +177,7 @@ void WinEDA_PcbFrame::Trace_Pcb( wxDC* DC, int mode )
DrawHightLight( DC, g_HightLigth_NetCode );
for( unsigned ii = 0; ii < m_Pcb->GetAreaCount(); ii++ )
for( int ii = 0; ii < m_Pcb->GetAreaCount(); ii++ )
{
ZONE_CONTAINER* edge_zone = m_Pcb->GetArea(ii);
edge_zone->Draw( DrawPanel, DC, wxPoint(0,0), mode);

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