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@ -78,37 +78,28 @@ EDA_ITEM* VIA::Clone() const |
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wxString VIA::GetSelectMenuText( EDA_UNITS aUnits ) const |
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{ |
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wxString format; |
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BOARD* board = GetBoard(); |
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wxString viaType; |
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switch( GetViaType() ) |
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{ |
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case VIATYPE::BLIND_BURIED: |
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format = _( "Blind/Buried Via %s %s on %s - %s" ); |
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break; |
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case VIATYPE::MICROVIA: |
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format = _( "Micro Via %s %s on %s - %s" ); |
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break; |
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// else say nothing about normal (through) vias
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default: |
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format = _( "Via %s %s on %s - %s" ); |
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break; |
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case VIATYPE::BLIND_BURIED: viaType = _( "Blind/Buried" ) + " "; break; |
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case VIATYPE::MICROVIA: viaType = _( "Micro" ) + " "; break; |
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default: viaType = _( "" ); break; |
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} |
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if( board ) |
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{ |
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// say which layers, only two for now
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PCB_LAYER_ID topLayer; |
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PCB_LAYER_ID botLayer; |
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LayerPair( &topLayer, &botLayer ); |
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return wxString::Format( format.GetData(), MessageTextFromValue( aUnits, m_Width ), |
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GetNetnameMsg(), board->GetLayerName( topLayer ), board->GetLayerName( botLayer ) ); |
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} |
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else |
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{ |
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return wxString::Format( format.GetData(), MessageTextFromValue( aUnits, m_Width ), |
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GetNetnameMsg(), wxT( "??" ), wxT( "??" ) ); |
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} |
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// say which layers, only two for now
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PCB_LAYER_ID topLayer; |
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PCB_LAYER_ID botLayer; |
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BOARD* board = GetBoard(); |
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LayerPair( &topLayer, &botLayer ); |
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return wxString::Format( _( "%s Via %s %s on %s - %s" ), |
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viaType, |
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MessageTextFromValue( aUnits, m_Width ), |
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GetNetnameMsg(), |
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board ? board->GetLayerName( topLayer ) : wxT( "??" ), |
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board ? board->GetLayerName( botLayer ) : wxT( "??" ) ); |
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} |
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@ -127,18 +118,18 @@ int TRACK::GetLocalClearance( wxString* aSource ) const |
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void TRACK::GetWidthConstraints( int* aMin, int* aMax, wxString* aSource ) const |
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{ |
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// No constraints if "this" is not (yet) linked to a board
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if( !GetBoard() ) |
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{ |
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*aMin = 0; |
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*aMax = INT_MAX; |
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return; |
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} |
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*aMin = 0; |
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*aMax = INT_MAX; |
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std::shared_ptr<DRC_ENGINE> drcEngine = GetBoard()->GetDesignSettings().m_DRCEngine; |
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DRC_CONSTRAINT constraint; |
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DRC_CONSTRAINT constraint = drcEngine->EvalRulesForItems( DRC_CONSTRAINT_TYPE_TRACK_WIDTH, |
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this, nullptr, GetLayer() ); |
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if( GetBoard() && GetBoard()->GetDesignSettings().m_DRCEngine ) |
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{ |
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BOARD_DESIGN_SETTINGS& bds = GetBoard()->GetDesignSettings(); |
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constraint = bds.m_DRCEngine->EvalRulesForItems( DRC_CONSTRAINT_TYPE_TRACK_WIDTH, this, |
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nullptr, GetLayer() ); |
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} |
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if( constraint.Value().HasMin() || constraint.Value().HasMax() ) |
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{ |
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@ -156,10 +147,6 @@ void TRACK::GetWidthConstraints( int* aMin, int* aMax, wxString* aSource ) const |
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int VIA::GetMinAnnulus( PCB_LAYER_ID aLayer, wxString* aSource ) const |
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{ |
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// No constraints if "this" is not (yet) linked to a board
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if( !GetBoard() ) |
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return 0; |
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if( !IsPadOnLayer( aLayer ) ) |
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{ |
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if( aSource ) |
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@ -168,10 +155,15 @@ int VIA::GetMinAnnulus( PCB_LAYER_ID aLayer, wxString* aSource ) const |
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return 0; |
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} |
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std::shared_ptr<DRC_ENGINE> drcEngine = GetBoard()->GetDesignSettings().m_DRCEngine; |
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DRC_CONSTRAINT constraint; |
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DRC_CONSTRAINT constraint = drcEngine->EvalRulesForItems( DRC_CONSTRAINT_TYPE_ANNULUS_WIDTH, |
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this, nullptr, aLayer ); |
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if( GetBoard() && GetBoard()->GetDesignSettings().m_DRCEngine ) |
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{ |
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BOARD_DESIGN_SETTINGS& bds = GetBoard()->GetDesignSettings(); |
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constraint = bds.m_DRCEngine->EvalRulesForItems( DRC_CONSTRAINT_TYPE_ANNULUS_WIDTH, this, |
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nullptr, aLayer ); |
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} |
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if( constraint.Value().HasMin() ) |
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{ |
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