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Added NETINFO_MAPPING, to ease saving nets with consecutive net codes (without modifying the net codes during the run time). Now, nets are saved with consecutive net codes (both modern & legacy plugins). Zones are saved together with their nets, without depending on the fact if there are any pads with such net. Therefore validation of zone net names was removed (pcbnew/class_board.cpp). Performed tests: - Changed a pad's net name from empty to existent - ok, name was changed. - Changed a pad's net name from empty to nonexistent - ok, error message is displayed, net name stays empty. - Changed a pad's net name from existent to empty - ok, net name became empty - Changed a pad's net name from existent to nonexistent - ok, error message is displayed, net name is not changed. - Drawn a zone that belongs to a net, then modified schematics so the net does not exist anymore. After reloading the net list, all pads/tracks are updated. Zones still belongs to the net that does not exist in the schematic (but still exists in .kicad_pcb file). After running DRC, the zone becomes not filled. - Undo & redo affects assignment of a polygon to a specific net (you may change net of a polygon, refill it and undo/redo the changes). - KiCad s-expr & legacy, Eagle, P-CAD boards seem to load without any problem (they also contain correct net names assigned to the appropriate pads). All types of board file formats were loaded, then saved in sexpr format and reopened with a KiCad built from the master branch (without my modifications). - A few boards were also saved using the legacy format and were opened with the master KiCad without any issues. - Change a net name for a pad, restore with undo/redo - ok - Remove everything, restore with undo - ok - Remove everything, reload netlist - ok Differences observed between files saved by the master branch KiCad and this one: - list of nets are not saved in any particular order, so net codes may differ - the default net class does not contain the unconnected net
12 years ago
Added NETINFO_MAPPING, to ease saving nets with consecutive net codes (without modifying the net codes during the run time). Now, nets are saved with consecutive net codes (both modern & legacy plugins). Zones are saved together with their nets, without depending on the fact if there are any pads with such net. Therefore validation of zone net names was removed (pcbnew/class_board.cpp). Performed tests: - Changed a pad's net name from empty to existent - ok, name was changed. - Changed a pad's net name from empty to nonexistent - ok, error message is displayed, net name stays empty. - Changed a pad's net name from existent to empty - ok, net name became empty - Changed a pad's net name from existent to nonexistent - ok, error message is displayed, net name is not changed. - Drawn a zone that belongs to a net, then modified schematics so the net does not exist anymore. After reloading the net list, all pads/tracks are updated. Zones still belongs to the net that does not exist in the schematic (but still exists in .kicad_pcb file). After running DRC, the zone becomes not filled. - Undo & redo affects assignment of a polygon to a specific net (you may change net of a polygon, refill it and undo/redo the changes). - KiCad s-expr & legacy, Eagle, P-CAD boards seem to load without any problem (they also contain correct net names assigned to the appropriate pads). All types of board file formats were loaded, then saved in sexpr format and reopened with a KiCad built from the master branch (without my modifications). - A few boards were also saved using the legacy format and were opened with the master KiCad without any issues. - Change a net name for a pad, restore with undo/redo - ok - Remove everything, restore with undo - ok - Remove everything, reload netlist - ok Differences observed between files saved by the master branch KiCad and this one: - list of nets are not saved in any particular order, so net codes may differ - the default net class does not contain the unconnected net
12 years ago
Added NETINFO_MAPPING, to ease saving nets with consecutive net codes (without modifying the net codes during the run time). Now, nets are saved with consecutive net codes (both modern & legacy plugins). Zones are saved together with their nets, without depending on the fact if there are any pads with such net. Therefore validation of zone net names was removed (pcbnew/class_board.cpp). Performed tests: - Changed a pad's net name from empty to existent - ok, name was changed. - Changed a pad's net name from empty to nonexistent - ok, error message is displayed, net name stays empty. - Changed a pad's net name from existent to empty - ok, net name became empty - Changed a pad's net name from existent to nonexistent - ok, error message is displayed, net name is not changed. - Drawn a zone that belongs to a net, then modified schematics so the net does not exist anymore. After reloading the net list, all pads/tracks are updated. Zones still belongs to the net that does not exist in the schematic (but still exists in .kicad_pcb file). After running DRC, the zone becomes not filled. - Undo & redo affects assignment of a polygon to a specific net (you may change net of a polygon, refill it and undo/redo the changes). - KiCad s-expr & legacy, Eagle, P-CAD boards seem to load without any problem (they also contain correct net names assigned to the appropriate pads). All types of board file formats were loaded, then saved in sexpr format and reopened with a KiCad built from the master branch (without my modifications). - A few boards were also saved using the legacy format and were opened with the master KiCad without any issues. - Change a net name for a pad, restore with undo/redo - ok - Remove everything, restore with undo - ok - Remove everything, reload netlist - ok Differences observed between files saved by the master branch KiCad and this one: - list of nets are not saved in any particular order, so net codes may differ - the default net class does not contain the unconnected net
12 years ago
  1. /*
  2. * This program source code file is part of KiCad, a free EDA CAD application.
  3. *
  4. * Copyright (C) 2012 CERN.
  5. * Copyright (C) 1992-2017 KiCad Developers, see AUTHORS.txt for contributors.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version 2
  10. * of the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, you may find one here:
  19. * http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
  20. * or you may search the http://www.gnu.org website for the version 2 license,
  21. * or you may write to the Free Software Foundation, Inc.,
  22. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
  23. */
  24. #ifndef KICAD_PLUGIN_H_
  25. #define KICAD_PLUGIN_H_
  26. #include <io_mgr.h>
  27. #include <string>
  28. #include <layers_id_colors_and_visibility.h>
  29. class BOARD;
  30. class BOARD_ITEM;
  31. class FP_CACHE;
  32. class PCB_PARSER;
  33. class NETINFO_MAPPING;
  34. /// Current s-expression file format version. 2 was the last legacy format version.
  35. //#define SEXPR_BOARD_FILE_VERSION 3 // first s-expression format, used legacy cu stack
  36. //#define SEXPR_BOARD_FILE_VERSION 4 // reversed cu stack, changed Inner* to In* in reverse order
  37. // // went to 32 Cu layers from 16.
  38. //#define SEXPR_BOARD_FILE_VERSION 20160815 // differential pair settings per net class
  39. //#define SEXPR_BOARD_FILE_VERSION 20170123 // EDA_TEXT refactor, moved 'hide'
  40. //#define SEXPR_BOARD_FILE_VERSION 20170920 // long pad names and custom pad shape
  41. //#define SEXPR_BOARD_FILE_VERSION 20170922 // Keepout zones can exist on multiple layers
  42. //#define SEXPR_BOARD_FILE_VERSION 20171114 // Save 3D model offset in mm, instead of inches
  43. //#define SEXPR_BOARD_FILE_VERSION 20171125 // Locked/unlocked TEXTE_MODULE
  44. #define SEXPR_BOARD_FILE_VERSION 20171130 // 3D model offset written using "offset" parameter
  45. #define CTL_STD_LAYER_NAMES (1 << 0) ///< Use English Standard layer names
  46. #define CTL_OMIT_NETS (1 << 1) ///< Omit pads net names (useless in library)
  47. #define CTL_OMIT_TSTAMPS (1 << 2) ///< Omit component time stamp (useless in library)
  48. #define CTL_OMIT_INITIAL_COMMENTS (1 << 3) ///< omit MODULE initial comments
  49. #define CTL_OMIT_PATH (1 << 4) ///< Omit component sheet time stamp (useless in library)
  50. #define CTL_OMIT_AT (1 << 5) ///< Omit position and rotation
  51. // (always saved with potion 0,0 and rotation = 0 in library)
  52. //#define CTL_OMIT_HIDE (1 << 6) // found and defined in eda_text.h
  53. // common combinations of the above:
  54. /// Format output for the clipboard instead of footprint library or BOARD
  55. #define CTL_FOR_CLIPBOARD (CTL_STD_LAYER_NAMES|CTL_OMIT_NETS)
  56. /// Format output for a footprint library instead of clipboard or BOARD
  57. #define CTL_FOR_LIBRARY (CTL_STD_LAYER_NAMES|CTL_OMIT_NETS|CTL_OMIT_TSTAMPS|CTL_OMIT_PATH|CTL_OMIT_AT)
  58. /// The zero arg constructor when PCB_IO is used for PLUGIN::Load() and PLUGIN::Save()ing
  59. /// a BOARD file underneath IO_MGR.
  60. #define CTL_FOR_BOARD (CTL_OMIT_INITIAL_COMMENTS)
  61. class DIMENSION;
  62. class EDGE_MODULE;
  63. class DRAWSEGMENT;
  64. class PCB_TARGET;
  65. class D_PAD;
  66. class TEXTE_MODULE;
  67. class TRACK;
  68. class ZONE_CONTAINER;
  69. class TEXTE_PCB;
  70. /**
  71. * Class PCB_IO
  72. * is a PLUGIN derivation for saving and loading Pcbnew s-expression formatted files.
  73. *
  74. * @note This class is not thread safe, but it is re-entrant multiple times in sequence.
  75. */
  76. class PCB_IO : public PLUGIN
  77. {
  78. friend class FP_CACHE;
  79. public:
  80. //-----<PLUGIN API>---------------------------------------------------------
  81. const wxString PluginName() const override
  82. {
  83. return wxT( "KiCad" );
  84. }
  85. const wxString GetFileExtension() const override
  86. {
  87. // Would have used wildcards_and_files_ext.cpp's KiCadPcbFileExtension,
  88. // but to be pure, a plugin should not assume that it will always be linked
  89. // with the core of the pcbnew code. (Might someday be a DLL/DSO.) Besides,
  90. // file extension policy should be controlled by the plugin.
  91. return wxT( "kicad_pcb" );
  92. }
  93. virtual void Save( const wxString& aFileName, BOARD* aBoard,
  94. const PROPERTIES* aProperties = NULL ) override;
  95. BOARD* Load( const wxString& aFileName, BOARD* aAppendToMe,
  96. const PROPERTIES* aProperties = NULL ) override;
  97. void FootprintEnumerate( wxArrayString& aFootprintNames, const wxString& aLibraryPath,
  98. const PROPERTIES* aProperties = NULL ) override;
  99. MODULE* LoadEnumeratedFootprint( const wxString& aLibraryPath, const wxString& aFootprintName,
  100. const PROPERTIES* aProperties = NULL ) override;
  101. MODULE* FootprintLoad( const wxString& aLibraryPath, const wxString& aFootprintName,
  102. const PROPERTIES* aProperties = NULL ) override;
  103. void FootprintSave( const wxString& aLibraryPath, const MODULE* aFootprint,
  104. const PROPERTIES* aProperties = NULL ) override;
  105. void FootprintDelete( const wxString& aLibraryPath, const wxString& aFootprintName,
  106. const PROPERTIES* aProperties = NULL ) override;
  107. long long GetLibraryTimestamp( const wxString& aLibraryPath ) const override;
  108. void FootprintLibCreate( const wxString& aLibraryPath, const PROPERTIES* aProperties = NULL) override;
  109. bool FootprintLibDelete( const wxString& aLibraryPath, const PROPERTIES* aProperties = NULL ) override;
  110. bool IsFootprintLibWritable( const wxString& aLibraryPath ) override;
  111. //-----</PLUGIN API>--------------------------------------------------------
  112. PCB_IO( int aControlFlags = CTL_FOR_BOARD );
  113. ~PCB_IO();
  114. /**
  115. * Function Format
  116. * outputs \a aItem to \a aFormatter in s-expression format.
  117. *
  118. * @param aItem A pointer the an #BOARD_ITEM object to format.
  119. * @param aNestLevel The indentation nest level.
  120. * @throw IO_ERROR on write error.
  121. */
  122. void Format( BOARD_ITEM* aItem, int aNestLevel = 0 ) const;
  123. std::string GetStringOutput( bool doClear )
  124. {
  125. std::string ret = m_sf.GetString();
  126. if( doClear )
  127. m_sf.Clear();
  128. return ret;
  129. }
  130. void SetOutputFormatter( OUTPUTFORMATTER* aFormatter ) { m_out = aFormatter; }
  131. BOARD_ITEM* Parse( const wxString& aClipboardSourceInput );
  132. protected:
  133. wxString m_error; ///< for throwing exceptions
  134. BOARD* m_board; ///< which BOARD, no ownership here
  135. const
  136. PROPERTIES* m_props; ///< passed via Save() or Load(), no ownership, may be NULL.
  137. FP_CACHE* m_cache; ///< Footprint library cache.
  138. LINE_READER* m_reader; ///< no ownership here.
  139. wxString m_filename; ///< for saves only, name is in m_reader for loads
  140. int m_loading_format_version; ///< which #SEXPR_BOARD_FILE_VERSION should be Load()ed?
  141. STRING_FORMATTER m_sf;
  142. OUTPUTFORMATTER* m_out; ///< output any Format()s to this, no ownership
  143. int m_ctl;
  144. PCB_PARSER* m_parser;
  145. NETINFO_MAPPING* m_mapping; ///< mapping for net codes, so only not empty net codes
  146. ///< are stored with consecutive integers as net codes
  147. void validateCache( const wxString& aLibraryPath, bool checkModified = true );
  148. MODULE* doLoadFootprint( const wxString& aLibraryPath, const wxString& aFootprintName,
  149. const PROPERTIES* aProperties, bool checkModified );
  150. void init( const PROPERTIES* aProperties );
  151. /// formats the board setup information
  152. void formatSetup( BOARD* aBoard, int aNestLevel = 0 ) const;
  153. /// formats the General section of the file
  154. void formatGeneral( BOARD* aBoard, int aNestLevel = 0 ) const;
  155. /// formats the board layer information
  156. void formatBoardLayers( BOARD* aBoard, int aNestLevel = 0 ) const;
  157. /// formats the Nets and Netclasses
  158. void formatNetInformation( BOARD* aBoard, int aNestLevel = 0 ) const;
  159. /// writes everything that comes before the board_items, like settings and layers etc
  160. void formatHeader( BOARD* aBoard, int aNestLevel = 0 ) const;
  161. private:
  162. void format( BOARD* aBoard, int aNestLevel = 0 ) const;
  163. void format( DIMENSION* aDimension, int aNestLevel = 0 ) const;
  164. void format( EDGE_MODULE* aModuleDrawing, int aNestLevel = 0 ) const;
  165. void format( DRAWSEGMENT* aSegment, int aNestLevel = 0 ) const;
  166. void format( PCB_TARGET* aTarget, int aNestLevel = 0 ) const;
  167. void format( MODULE* aModule, int aNestLevel = 0 ) const;
  168. void format( D_PAD* aPad, int aNestLevel = 0 ) const;
  169. void format( TEXTE_PCB* aText, int aNestLevel = 0 ) const;
  170. void format( TEXTE_MODULE* aText, int aNestLevel = 0 ) const;
  171. void format( TRACK* aTrack, int aNestLevel = 0 ) const;
  172. void format( ZONE_CONTAINER* aZone, int aNestLevel = 0 ) const;
  173. void formatLayer( const BOARD_ITEM* aItem ) const;
  174. void formatLayers( LSET aLayerMask, int aNestLevel = 0 ) const;
  175. };
  176. #endif // KICAD_PLUGIN_H_